Simple PRNG problem -> clk not recognised as input

Hi

I wanted to sythesize a simple PRNG which is implemented as a LFSR. However, the problem is that when I debug the implemnetation on the chip I always get the same random value which are the last two bits of the tmp varible. So in my case its always 01. Can anyone tell me what I am missing? Because in simulation it works. The strange thing is that ISE 10.1 tells me XST:647: INPUT is never used. This port will be preserved abd left unconnected if it belongs to a top-level block. But I have surely connected the clk and also need it in the process for the PRNG?

entity Testbench is port( clk : in std_logic; dbg_R0 : inout std_logic; dbg_R1 : inout std_logic ); end Testbench;

architecture Behavior of Testbench is

component PRNG is port ( clk : in std_logic; R0 : out std_logic; R1 : out std_logic ); end component;

begin

--LEFT OUT SOME CODE FOR CHIPSCOPE DEGGUGING

ARCH_PRNG:PRNG port map( clk => clk, R0 => dbg_R0, R1 => dbg_R1 );

end architecture Behavior;

entity PRNG is port ( clk : in std_logic; R0 : out std_logic; R1 : out std_logic ); end PRNG;

architecture Behavior of PRNG is

begin process(clk) variable temp : std_logic_vector(7 downto 0) := B"01110101"; begin temp := (temp(1) xor temp(0)) & temp(7 downto 1); R0

Reply to
Dan Arik
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Thats not right, Chipscope tells me that the last two bits are always 0....

Reply to
Dan Arik

alright, it seems that i have to use the clk signal explicily again in the process itself that it acitvates....

So if I use a if clk'event and clk='1' then it works

Reply to
Dan Arik

The reason that ISE is telling you that is never used is that you never used the clk.

What you're looking for probably looks more like this:

process(clk) variable temp : std_logic_vector(7 downto 0) := B"01110101"; begin if rising_edge(clk) then temp := (temp(1) xor temp(0)) & temp(7 downto 1); R0

Reply to
Rob Gaddi

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