Hi I'am a newbe, and know how to add unsigned numbers in Verilog HDL, but how to define a signed number? I've the following situation:
reg [7..0] p1 //(is an unsigned value from AD converter) 0..255 reg [7..0] p2 // is the unsigned value that we should have 0..255
now I want to substract p1-p2, to have the differenz, to correct the error reg[7..0] diff //should be a signed value
how do I define this in Verilog HDL
best regards remo
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