I would like to assign TEMP value to RESULT at symbol_clk_edge and reset TEMP to SAMPLE_IN value. The most important for me is to store last value of TEMP to RESULT before resetting it.
I'll try using it again as I did write originally. I had some problems with this implementation though. That's why I've posted the question. Sometimes at symbol_clk_edge, RESULT would be assigned with SAMPLE_IN (bad), and sometimes with TEMP as I want it. But also, it looked like there was no delay between SAMPLE_IN and RESULT or TEMP!! maybe because of that? SAMPLE_IN is a port TEMP, RESULT are signals. ?? I'll try assigning port to signal first. Maybe it will create a proper 1 CLK delay.
Hope that helps