I am having difficulty solving a timing problem using a Spartan 3 embedded platform. We are using a MicroBlaze core with some user IP modules and some Xilinx modules attached through the OPB bus. One of the IP modules is a 3-wire serial data interface. We have to be able to generate multiple protocols so this module handles all of that. The "data" line is bidirectional. It is connected correctly to a bidirectional buffer at the top level. We write data to a "part" and then can read that data back from the part. The part sends back a bit of data on the FPGA's "data_clock" rising edge. The FPGA clocks that data in on the falling edge of the "data_clock" signal. All was working fine unitl we placed an extension board on our platform. This effectively makes the external path from the "part" to the FPGA much longer. The readback does NOT work when using this board. The FPGA reads back data, but not the correct data.
There are test points on our platform that allow us to look at the
3-wire interface signals in between the part and the FPGA. These signals look fine (with respect to timing) when using the board that works and the one that doesn't. It seems that the critical delay is happening in the FPGA. It seems like the data going in to the pin is not getting to the module IP logic before the critical clock edge occurs. Is there a way to tell the Xilinx tools (via UCF constraints) to constrain that path to a certain time spec?Another problem is that I have looked at the ngc file for the EDK-produced wrapper for my module. The correct three signals ("data_O", "data_I", and "data_T") are I/O pins on the module, but once I dive down into the mapped implementation, the "data_I" is not longer anywhere to be found! I don't know where it goes, so I can't find a net name or anything like that to constrain! What is going on there?
Thanks....