Signal is assigned but never used. XST Warning help

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Hello,

I am currently working on a Verilog module within ISE and Modelsim, and
within this module it gives me the error:  Signal <foo> is assigned but
never used.

I currently have a 2D array that is holding data for me, and I access
this data within a task, which is called from another block when I need
to compare the new incoming data with the older data, and
update/replace as needed. The way that I am trying to get that done is
close to this example code I had written:

-----------------------------------------------------------------------------------------
module top_mod(
        input clk,
        input switch_i,
        input [2:0] addr_i,
        output reg [3:0] data_o
        );


reg [3:0] data0 = 4'b0000;
reg [3:0] data1 = 4'b0001;
reg [3:0] data2 = 4'b0010;
reg [3:0] data3 = 4'b0011;
reg [3:0] data4 = 4'b0100;
reg [3:0] data5 = 4'b0101;
reg [3:0] data6 = 4'b0111;
reg [3:0] data7 = 4'b1000;

reg [3:0] data_array [7:0];

reg [3:0] data_hold;


always @(posedge clk)
begin
    if (switch_i)
        switch_on;
    else
        data_o = data_o;
end


task switch_on;
begin
    data_hold = data_array[addr_i];
    data_o = ;
end
endtask

endmodule
-----------------------------------------------------------------------------------------

In this example I am not writing back to the array, but you get the
basic idea, and this does give me the "Signal <data_hold> is assigned
but never used." error. Does anyone know why this is happening, or
perhaps a better way to read out part of a vector in a 2D array? Let me
know if any more info is needed. Thanks for any help!

-Mark


Re: Signal is assigned but never used. XST Warning help

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Synthesis will optomize out anything that does not factor into the equations
for an output pin of the TOP level entity.  For example, if your top level
entity has no outputs then everything will get optomized away.  Even though
you may be assigning to signal 'data_hold', if 'data_hold' is not an output
of the top level entity itself or it does not cause any changes in any of
the outputs that you do have then they will get optomized away and result in
the warning that you're seeing.

Check your code for places where you use 'data_hold' and see where the path
to the output pins of the device breaks down.

KJ



Re: Signal is assigned but never used. XST Warning help
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It looks like data_hold[3] is assigned but never used. In the task, you
assign all 4 bits of data_hold, but only bits [2:0] are used to form
data_o. XST reports individual bits that are assigned but not used, so I
would expect to see:
WARNING:Xst:646 - Signal <data_hold<3>> is assigned but never used.