Shutdown parts of core logic on FPGA

Hi NG.

I would like to know if it would be possible to shutdown (cut the power) from some parts of the core logic on an FPGA while other parts are still running?

Like, could I have an internal timer turning the power on/off to some calculus-logic in given time periods?

So parts of my question is what happens if not all the VCC (core) pins on the chip is supplied? Is it intuitive to know which power-rails these inputs serve?

Has anybody any experience with doing stuff like this and could you give my some advice/suggestions?

Best Regards HG

Reply to
H G
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H G schrieb:

AFAIk this is not possible. When you want to save power, use a clock MUX to disable the clock.

They are connected internally.

Regards Falk

Reply to
Falk Brunner

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