Maybe my description was a bit confusing, sorry for this. The clocks really are asychronous. There is no stable phase relationship between them, since the 27MHz clock is the ouput of a PLL locked on the H-Sync of a video signal, and the 108MHz system clock is derived from a 27MHz crystal oscillator.
If you pick the right xilinx you could multiply the 27MHz up to 108MHz internally. Just use the internal PLL
Simon
I'm guessing this is video. If that is the case, you've probably got an incoming pixel clock and data that is timed to that clock that you want to get on to the internal 108 MHz clock. In an ideal world, you could use the DLLs to multiply the pixel clock by 4 to get your internal clock. Unfortunately, the pixel clock from most of the popular decoders has far too much jitter to keep the DLLs happy, so you are more or less forced to use an unrelated local clock.
So how to do it? Clock your incoming pixel data into the FPGA on the 27 Mhz pixel clock, and also toggle an additional flag bit. A change on the flag bit corresponds to new data getting clocked in. Synchronize that flag bit output to the 108 Mhz clock using a single flip-flop, then detect the change in the synchronized flag with a synchronous edge detect state machine. I use a state machine designed so that only one bit is sensitive to the synchronized toggle signal and which generates a 1 clock wide pulse in response to a level change on the toggle input. For low clock rates, you can do without the synchronizing flip flop preceding the state machine because the toggle input only effects one state bit. The state machine I use is:
case state is when "00" =>
if sync='1' then next_state I need to synchronize an incoming 27MHz signal (50% duty cycle) with
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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759
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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759
Nope, Jitter out of the video decoders is about 10x what is allowed by the DLL/DCM. I posted earlier a solution that works fine for this, and is used in a number of my customer's products.
Sim> If you pick the right xilinx you could multiply the 27MHz up to 108MHz
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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759
Have a talk to your friendly Xilinx Apps engineer Spartan 3's can tolerate a high jitter (So I've read) .. they just wont tell you that except under NDA.
Simon
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times
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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759
:You should always be concerned about metastability, whenever :asynchronous signals are being synchronized. Let me add some numbers to :Phil Freidin's excellent comments: : :Metastability creates unpredictable additional settling delays (even :oscillations can be considered delays to valid out). The probability of :a specific max delay depends on the clock rate, the data rate, and the :IC technology. : [snip]
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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759
Xilinx guys : wouldn't it be cool to integrate such a resynchronizer circuit in each IOB ?
Yea. It's called a flipflop. There is already one there.
-- Phil Hays
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