Shift register example?

probably something like

--------------------------------- signal cpt : integer range 0 to 15; --i'm not sure for this declaration usually i use only std_logic with convertion signal temp : std_logic_vector( 15 downto 0);

process(clk) begin if rising_edge(clk) then cpt in VHDL.

Well, there are some issues with this code example:

1) The reset is missing, this is a problem for the simulation

2) integer based counters tend to not wrap arount automatically, I do not know for sure what synthesis might result, but simulation will fail

3) While the general behavior is ok with the above points corrected, this is not a shift register. Sorry. See notes below.

Try again! Chris

KCL wrote:

this is ok

Missing reset here, initialize cpt here!

Parallel loadable register. ok.

thanks for note

1) integer count : usually i use std_logic for all my signal and use conversion function for arithmetic, so i have no problem of wrap around,

2) reset missing : does at startup all signal have a value unknow but equal to '1' or '0' so after max 16cycles cpt should back to 0 so there is a 16 cycle clock intial time that (depend of your application need but in most of DSP) is not important I think.

Also for reset what is the best synchronous or asynchronous?? because synchronous reset seems to need less ressource??

3)not a shift register but i think this not a real shift register he wanted :"parallel in serial out latching shift register" for me he asked for serializator (sorry my english is so bad so I translate as I can) if i wanted to do a shift register i will have done:

data_reg

I made a mistake shift register is :

That's right.

I do not agree with you here: what is "XXXX" + 1 ? I had a lot of simulations which did not start properly because of wrong initial values.

Well in hardware all would work, but your simulation still differs in behaviour. This is mainly because hardware does not have the "XXXX" value. Since we are here in the FPGA news group, all FPGAs I know of initialize with zero, unless other values are set.

I have read a lot about resets in this newsgroup and I really do not understand why so few people use the "reset on configuration": When you download the bitstream everything has its default, so what else do you want? You can just program it as asynchronous reset and the tools do the rest (nearly).

Yes you are right, the task is not completely mentioned. I just wanted to correct the source code, sorry for the harsh tone.

Best regards, Chris

Hi FYI I found this on the web and it is the same part that I use when I do this with hardware. However like the real part there is no reset. Do you think that the lack of reset condition will cause problems other than simulation with an unknown initial condition on the serial output pin? As for the use it is to impliment a simple SPI output of a 16 bit counter that I had sent to a seven segment decoder than an lcd but now want to transfer into my PC. Thanks

--

-- ls165.vhd

--

-- Description: This is a VHDL synthesizable description of the

74LS165

-- 8-Bit Parallel-to-Serial Shift Register.

--

--
-- Author:  Wilson Li
-- Date:    March 27, 1997

The reset on configuration is not guaranteed to be fast enough (in all chips) to bring everything out of reset at the same time. This can cause problems if your code expects this. Xilinx specifically recommends that you not use GSR in the Virtex, at least, because of the amount of skew.

In addition - I'm not clear whether asynch. resets are covered by timing analysis. If it's not, then that leads to the same problem. Somebody else might be better equipped to comment on this.

Jeremy

For reset as Chris says if there is no reset you will have problem for simulate

There is some problems in the code there is no counter to control the load of the data so you must take care when p is set to 1 (this is the condition for load ) and when the data will have been sent you will send ds signal so be sure of what you wanna sent after your data word and finnally preferably than writing

So if i use asynchronous reset, all internal signal will be set at the reset value at the startup of the fpga??

I have check , and I have nothing else to add that you are right, little padawan have a lot to learn^^ I have dl the xilinx synthesis design guide, now let's read it (400p ->thales's guide was smaller... : ~ )

No problem for the "the harsh tone", I just have some problem with critics even more actually because I'm tired of those french firm that take no risk with young graduates like me and prefer older engineer without skill. :#

Regards

Alexis