Hello! I am using the WebPack ( VHDL ) and the 9500 family CPLD. I would like to make a SPI interface. So now I need a VHDL description of an 8 bit parallel-in serial-out shift register with MSB shifting out first. So far I haven't had any luck so I am asking you for help. I thank you in advance for your efforts.
Best regards George Mercury
You need to do a little work bud. Go to the Xilinx website and read through some of the application notes. Also, in Webpack, find a menu entry called "Library Templates". This is FULL of all sorts of examples and templates you can use. You can even do a Google/Yahoo/whatever search of this newsgroup and/or the 'net in general and find loads of examples and tutorials on FPGA's, Verilog, VHDL and other topics.
There's no such thing as a dumb question, but I think that most newsgroup participants appreciate it when a poster does a little bit of work before asking for help.
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"
Here's what I cooked up:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- 8-bit load, 1-bit shift out (msb first)
--
-- if load is '1', a new value is loaded from d.
-- if shift_out is '1', next bit is shifted out (msb first).
-- entity shft4_1 is port (d: in std_logic_vector(7 downto 0); load: in std_logic; shift_out: in std_logic; clk: in std_logic; reset: in std_logic; q: out std_logic ); end entity;
architecture Behavioral of shft8_1 is signal data: std_logic_vector(7 downto 0); begin process (d, load, clk, reset) begin if reset = '1' then data
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