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SGMII, xps_ll_temac and MDIO / MCD

Hi,

I'm attempting to get the xps_ll_temac talking to an SGMII PHY (Vitesse 8211), with little success.

The board doesn't have a dedicated 125MHz differential clock, so I'm deriving the 125MHz clock internally with a DCM, driving the ll_temac's MGTCLK_P signal with it, and setting the C_INCLUDE_IO param to zero to direct EDK that this clock drives the MGT clock directly (no IBUFDS). I understand this is not ideal but I didn't lay out the board!

The C_TEMAC0_PHYADDR param is set to the default 0b00001, and when I do a PHY address scan I can see the internal Rocket IO phy at this address. I can read the MII mgmt interface regs at this PHY address, and they correspond with the values expected for the SGMII / 1000BaseX internal Phy as described in the ll_temac datasheet (Tables 62-73 in the DS).

However, despite having wired up the MDIO and MDC pins on the board to the external PHY and connected to the ll_temac, and having strapped the PHY's relevant config pins to give a PHY address of 0b01000, the phy address scan turns up nothing.

It's not clear to me if, when using SGMII or 1000BaseX, the external PHY's MII registers should also be visible, in addition to the RocketIO PHY.

A quote from the datasheet doesn't really clarify:

"The MII Management inteface is used ...in the case of SGMII...to access PHY registers internal to the Hard TEMAC silicon component..."

This suggests there's no "pass through" to the MII interface on the board (MDIO / MCD). In that case, how can I talk to the PHY chip's MIIM interface to get it into the correct configuration?

Here's the values I see on MII registers 0-31 on PHY address 0b00001 (the internal RocketIO phy). They correspond to the expected values.

0: 1140 1: 01C8 2: 0028 3: D400 4: 0001 5: 8001 6: 0004 7: 2001 8: 0000 9: 0000 10: 0000 11: 0000 12: 0000 13: 0000 14: 0000 15: 8000 16: 0003 17: 0000 18: 0000 19: 0000 20: 0000 21: 0000 22: 0000 23: 0000 24: 0000 25: 0000 26: 0000 27: 0000 28: 0000 29: 0000 30: 0000 31: 0000

Any advice or input greatly appreciated. Even better would be a reference design using the ll_temac in SGMII mode. The cosest I've found is an old EDK8.2 era ML410 SGMII design, that uses the earlier incarnation of the TEMAC cores (not ll_temac).

Thanks,

John

Reply to
John Williams
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Did you consider the jitter requirements when using the DCM to generate the clock for the MGT?

I've used 9.1 w/ the ML410 and the SGMII ethernet and the plb_temac. I have not tried to yet on 9.2 w/ the new xps_ll_temac, but the old version did not support SGMII. One item of note is make sure you have all the necessary clocks hooked up (or disconnected). I recently ran into an issue where I had the GTX_CLK connected to the hard_temac in

9.1 and my MII interface was not working. Found out that it was because that clock was not to be connected when using only a MII interface.

HTH, Mike

Reply to
morphiend

I've got it working now. I obtained an ML505 SGMII reference design from Xilinx, and reworked it to derive the MGT clock from an internal DCM rather than the external differential clock - worked fine! Gave me confidence that my clocking scheme would work, which it does.

For the record, my problem was needing some pullup and pulldown constraints on some FPGA pins sampled by the PHY immediately post- reset. The PHY oscillator was being disabled, - no clock -> no fun!

One observation from this experience - with the proliferation of BGA packaging there are a lot of signals that simply cannot be observed if they route directly between two BGA packages with no discretes touching the trace. Instead of directly observing the clock I had to route it into the FPGA, through a big counter and drive a LED with the MSB to detect activity.

Cheers,

John

Reply to
John Williams

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