SGMII with Virtex 4 embedded MAC

Hi everyone.

I'm trying to implement a gigabit ethernet mac connected to a external gigabit PHY using a SGMII link.

I've used the coregen wrapper generator (v4.1 + the patch in answer record 22332 and the new calibration block 1.4.1) to generate an example design that I've slighty modified to fit my need. The mais modifications are : - Connect the EMAC client interface to some packet generator - Change some PLL and DCM settings to fit my reference frequency which is 250MHz instead of the 125MHz using in the example design. - Bypassed the internal AC coupling of the rocket io (already done using external components) - Activated the PCS/PMA Autonegotiation (tieoff pins).

The problem I'm having is that nothing is received nor send.

I see that the DCM lock and so does the pll of the rocketio. When I look at the interface of the rocket io : - On the TX side, I see the EMAC sending the correct stuff when trying to send a packet : /SFD/ = *0xFB = 0x55 0x55 0x55 0x55 0x55 = 0xD5 = .... = 0x?? 0x?? 0x?? 0x?? *0xFD *0xF7

and when doing nothing is sends IDLEs *0xBC 0x50

- On the RX side, I see the MAC keeping sending it's configuration register

*0xBC 42 01 98 *0xBC B5 01 98 ....

I haven't found really clear SGMII doc, but from what I understand, the PHY sending it's configuration means it's not in "data-mode" because it's awaiting the SGMII autonegotiation process to take place, but the MAC is already in data mode. And the mac is supposed to answer to the configuration registers sent by the phy or am I wrong ?

The components i'm using are : - The DiniGroup DVI card :

formatting link
which has a V4FX60 CES4 and numerous rocket io on SMA. - The xilinx phy daughter card :
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which has two marvell alaska PHY connected to SMA.

The two board are connected using SMA cables (and nothing else, the MDIO interface of the PHY is not connected) and the phy card has been configured thru jumpers to be in sgmii mode at reset.

Thanks for any help,

Sylvain

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Sylvain Munaut
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