I'm a student working an a Altera EPXA1F484C1 FPGA, and I'm having some problems I hope someone can help me with.
- Is there a way to tell Quartus that the project I'm compiling is ment as a "internal" building block, meaning that the pins isn't actual device pins, but "internal pins"? I'm wondering since I have several "internal blocks" with 128 bits in and out, and Quartus stops my compilings complaining that the device I'm compiling for has to few pins for my design.
- I get stuck-at errors...and I have no idea why. I get this warning: "Warning: No clock transition on AESRoundSP- 2:inst|lpm_dff0:inst5|lpm_ff:lpm_ff_component|dffs[127] register" And this continues for all 128 flipflops. But they are clocked by the "master clock". I have not created a clock signal, but the clock is named clk, and then Quartus should assume that the signal is a clock, right? Anyway, Quartus compiles my design without errors, but the summary tells me that I'm not using any LEs or any memory bits...
The AESRoundSP-2 is a building block in a larger design, but does not compile "on its own" because it uses too many pins and memory bits. Can this cause the weird error in (2)?