How does one set the environmental variable in ISE 7.1? The following error message was obtained:
ERROR:Place:645 - A clock IOB clock component is not placed at an optimal clock IOB site The clock IOB component is placed at site IOB_X1Y48. The clock IO site can use the fast path between the IO and the Clock buffer/GCLK if the IOB is placed in the master Clock IOB Site. If this sub optimal condition is acceptable for this design you may set the environment variable XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING to demote this message to a WARNING and allow your design to continue.
The Xilinx support solution is:
This error warns that you are not using optimal clock resources.
The error occurs when the Clock input is Locked to either the N side of a Differential Pair of Clock Capable I/O or to a Low Capacitance input, because this results in a local route and causes additional delay.
If this routing is acceptable, then the XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING environment variable should be set; this will relegate the error to a warning.
If this routing is not acceptable, then the Clock should use either the P input of a Clock Capable I/O or a Global Clock input.