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Serial LVDS ADC to spartan6

I have to connect a dual 12-bit ADC with serial LVDS outputs (2-lanes per converter) to a spartan 6 FPGA. It would be ideal if I can use a single HDMI connector for this.

The converters I'd like to use are the ADS6224 or ADC12S105, running at

100 MHz sample rate. They have 6 data LVDS data outputs: 4 data lines, 1 frame clock and 1 bit clock.

Since the HDMI connection only has 5 differential pairs (including the HEC data lines) I had the idea to not connect the bit clock, but instead use the FPGA's DCM to reconstruct the bit clock from the frame clock.

Any comments on this idea? Could that work?

Thanks, Thomas

Reply to
Thomas Heller
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I think it could work, it would be similar to camera-link

-Lasse

Reply to
langwadt

converter) to a spartan 6 FPGA. It would be ideal if I can use a single HD MI connector for this. The converters I'd like to use are the ADS6224 or AD C12S105, running at 100 MHz sample rate. They have 6 data LVDS data outputs : 4 data lines, 1 frame clock and 1 bit clock. Since the HDMI connection on ly has 5 differential pairs (including the HEC data lines) I had the idea t o not connect the bit clock, but instead use the FPGA's DCM to reconstruct the bit clock from the frame clock. Any comments on this idea? Could that w ork? Thanks, Thomas

For that to work, the frame clock from the ADC must be continuous with no g aps or phase changes between output words. Otherwise, the PLL will not be a ble to lock on instantly to each word. You will also not be able to read th e first several (tens/hundreds/thousands of?) words from the ADC while the PLL locks onto the frame clock.

Andy

Reply to
jonesandy

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