Serial Input Review and Questions

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The included code is used to search a serial stream for a sync word and then set
a data valid flag for the sync word and the next four words in the stream.
Simulation works fine but the post-place and route simulation fails to set the
data valid flag. I am assuming that this is a timing problem in detecting the
sync pattern but not sure how to correct it.

In addition ISE generates three warnings that I am not sure how to resolve.

If anyone has the time to look this code over and offer suggestions?

Thanks, Joel

---Code library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity downlink is

    generic    ( SR_WIDTH             : integer := 8 );

Port         (    rst : in std_logic;         sio_clk : in std_logic;         sio_data : in
std_logic;         data_valid : out std_logic;         sio_word : out
std_logic_vector(SR_WIDTH-1 downto 0)); end downlink;

architecture RTL of downlink is

    constant        SYNC_WORD : std_logic_vector(7 downto 0) := X"D5";

    type            t_SioState is ( SYNC, LOAD );

    signal        s_sio_word        : std_logic_vector(SR_WIDTH-1 downto 0);
    signal        s_data_valid    : std_logic;

    begin

    process ( sio_clk, rst )

        variable        bit_count         : integer range 0 to 8;         variable        word_count        :
integer range 0 to 4;

        variable        SioState : t_SioState;

        variable        v_sio_word        : std_logic_vector(SR_WIDTH-1 downto 0);
        variable        v_data_valid    : std_logic;

    begin

        if ( rst = '1' ) then

            SioState            := SYNC;

            v_sio_word        := ( others => '0');             v_data_valid    := '0';

            bit_count        := 0;             word_count        := 0;

        elsif ( falling_edge( sio_clk )) then

            v_sio_word         := v_sio_word(SR_WIDTH-2 downto 0) & sio_data;             v_data_valid
    := '0';

            case SioState is

                when SYNC =>

                    if ( v_sio_word = SYNC_WORD ) then

                        v_data_valid     := '1';                         SioState         := LOAD;

                    end if;

                when LOAD =>

                    bit_count := bit_count + 1;

                    if ( bit_count = 8 ) then

                        v_data_valid     := '1';                         bit_count        := 0;

                        word_count         := word_count + 1;

                        if (word_count = 4 ) then

                            word_count    := 0;                             SioState        := SYNC;

                        end if;

                    end if;

            end case;

            s_sio_word        <= v_sio_word;             s_data_valid    <= v_data_valid;

        end if;

    end process;            

    sio_word        <= s_sio_word;     data_valid    <= s_data_valid;

end RTL;

--Test Bench USE std.textio.all; USE ieee.std_logic_textio.all;

ENTITY downlink_tb_vhd IS END downlink_tb_vhd;

ARCHITECTURE behavior OF downlink_tb_vhd IS

    -- Component Declaration for the Unit Under Test (UUT)     COMPONENT downlink
    PORT(         rst : IN std_logic; --        sys_clk : IN std_logic;         sio_clk : IN
std_logic;         sio_data : IN std_logic;         data_valid : OUT std_logic;         sio_word :
OUT std_logic_vector(7 downto 0)         );     END COMPONENT;

    --Inputs     SIGNAL rst : std_logic := '1'; --    SIGNAL sys_clk : std_logic := '0';
    SIGNAL sio_clk : std_logic := '0';     SIGNAL sio_data : std_logic := '0';

    --Outputs     SIGNAL data_valid : std_logic;     SIGNAL sio_word : std_logic_vector(7
downto 0);

BEGIN

    -- Instantiate the Unit Under Test (UUT)     uut: downlink PORT MAP(         rst => rst,
--        sys_clk => sys_clk,         sio_clk => sio_clk,         sio_data => sio_data,
        data_valid => data_valid,         sio_word => sio_word     );

--    sys_clk <= not sys_clk after 10 ns;

    tb : PROCESS

    FILE infile : Text;

    variable inline : LINE;     variable in_val : integer;     variable data :
std_logic_vector(31 downto 0);

    BEGIN

        -- Wait 100 ns for global reset to finish         wait for 100 ns;         rst <= '0';

        file_open( infile, "D:/VHDL/DOWNLINK/VECTOR.DAT", READ_MODE );

        loop

            if ( endfile( infile )) then                 assert false                     report "End of Vector
File"                     severity NOTE;                 exit;             end if;

            readline ( infile, inline );             hread ( inline, data );

            for i in 31 downto 0 loop

                si

Re: Serial Input Review and Questions
Files attached - Seems my newsreader at work cut off the files.

Joel

Quoted text here. Click to load it


begin 666 vector.dat
M9#!A9#4S9#4-"D8P1C!&1#-%#0I&,$8P1D8U1 T*-35$-3E&-44-"CDP,# P
#,# P
`
end

begin 666 downlink.vhd
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2T-"BTM($-O;7!A
M;GDZ( T*+2T@16YG:6YE97(Z#0HM+0T*+2T@0W)E871E($1A=&4Z(" @(#$T
M.C(Q.C(W(# U+S$W+S U#0HM+2!$97-I9VX@3F%M93H@(" @#0HM+2!-;V1U
M;&4@3F%M93H@(" @9&]W;FQI;FL@+2!"96AAFE%O<F%L#0HM+2!0<F]J96-T
M($YA;64Z(" @#0HM+2!487)G970@1&5V:6-E.B @#0HM+2!4;V]L('9E<G-I
M;VYS.B @#0HM+2!$97-C<FEP=&EO;CH-"BTM#0HM+2!$97!E;F1E;F-I97,Z
M#0HM+2 -"BTM(%)EFE%S:6]N.@T*+2T@4F5V:7-I;VX@,"XP,2 M($9I;&4@
M0W)E871E9 T*+2T@061D:71I;VYA;"!#;VUM96YT<SH-"BTM( T*+2TM+2TM
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2T-"FQI8G)A<GD@245%13L-
M"G5S92!)145%+E-41%],3T=)0U\Q,38T+D%,3#L-"@T*#0IE;G1I='D@9&]W
M;FQI;FL@:7,-"@T*"6=E;F5R:6,)*"!34E]724142" )"0DZ(&EN=&5G97(@
M.CT@." I.PH-"B @(%!O<G0@"0DH"7)S=" Z(&EN('-T9%]L;V=I8SL-"B @
M(" @(" @(" @"0ES:6]?8VQK(#H@:6X@<W1D7VQO9VEC.PT*(" @(" @(" @
M(" )"7-I;U]D871A(#H@:6X@<W1D7VQO9VEC.PT*(" @(" @(" @(" )"61A
M=&%?=F%L: snipped-for-privacy@.B!O70%@<W1D7VQO9VEC.PT*(" @(" @(" @(" )"7-I;U]W
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M,"DI.PT*96YD(&1O=VYL:6YK.PT*#0IA<F-H:71E8W1U<F4@4E1,(&]F(&1O
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M#0H)"65L<VEF("@@9F%L;&EN9U]E9&=E*"!S:6]?8VQK("DI('1H96X-"@D-
M"@D)"79?<VEO7W=O<F0@"0DZ/2!V7W-I;U]W;W)D*%-27U=)1%1(+3(@9&]W
M;G1O(# I("8@<VEO7V1A=&$[#0H)"0EV7V1A=&%?=F%L:60@"3H]("<P)SL-
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M"0D)"0EV7V1A=&%?=F%L:60@"3H]("<Q)SL-"@D)"0D)"5-I;U-T871E( D)
M.CT@3$]!1#L-"@T*"0D)"0EE;F0@:68[#0H-"@D)"0EW:&5N($Q/040@/3X-
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M"0D)"7=O<F1?8V]U;G0@"0DZ/2!W;W)D7V-O=6YT("L@,3L-"@T*"0D)"0D)
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M9%]C;W5N= DZ/2 P.PT*"0D)"0D)"5-I;U-T871E"0DZ/2!364Y#.PT*"0D)
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`
end

begin 666 downlink_tb.vhd
M#0HM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+0T*+2T@0V]M
M<&%N>3H@#0HM+2!%;F=I;F5E<CH-"BTM#0HM+2!#<F5A=&4@1&%T93H@(" Q
M-#HU-#HT.2 P-2\Q-R\R,# U#0HM+2!$97-I9VX@3F%M93H@("!D;W=N;&EN
M:PT*+2T@36]D=6QE($YA;64Z(" @9&]W;FQI;FM?=&(NFA%D#0HM+2!0<F]J
M96-T($YA;64Z("!$;W=N;&EN:PT*+2T@5&%R9V5T($1EFE%C93H@( T*+2T@
M5&]O;"!V97)S:6]N<SH@( T*+2T@1&5S8W)I<'1I;VXZ(" @#0HM+2 -"BTM
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M;W=N;&EN:PT*+2T-"BTM($1E<&5N9&5N8VEE<SH-"BTM( T*+2T@4F5V:7-I
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M9%]L;V=I8U]V96-T;W(H,S$@9&]W;G1O(# I.PT*#0H)0D5'24X-"@T*"0DM
M+2!786ET(#$P,"!N<R!F;W(@9VQO8F%L(')E<V5T('1O(&9I;FES: T*"0EW
M86ET(&9O<B Q,# @;G,[#0H)"7)S=" \/2 G,"<[#0H-"@D)9FEL95]O<&5N
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M7TU/1$4@*3L-"@T*"0EL;V]P#0H-"@D)"6EF("@@96YD9FEL92@@:6YF:6QE
M("DI('1H96X-"@D)"0EA<W-E<G0@9F%L<V4-"@D)"0D)<F5P;W)T(")%;F0@
M;V8@5F5C=&]R($9I;&4B#0H)"0D)"7-EF5%R:71Y($Y/5$4[#0H)"0D)97AI
M=#L-"@D)"65N9"!I9CL-"@T*"0D)<F5A9&QI;F4@*"!I;F9I;&4L(&EN;&EN
M92 I.PT*"0D):')E860@*"!I;FQI;F4L(&1A=&$@*3L-"@T*"0D)9F]R(&D@
M:6X@,S$@9&]W;G1O(# @;&]O< T*#0H)"0D)<VEO7V-L:R \/2 G,2<[#0H)
M"0D)<VEO7V1A=&$@/#T@9&%T82AI*3L-"@D)"0EW86ET(&9O<B U,"!N<SL-
M"@D)"0ES:6]?8VQK(#P]("<P)SL-"@D)"0EW86ET(&9O<B U,"!N<SL-"@T*
M"0D)96YD(&QO;W [#0H-"@D)96YD(&QO;W [#0H-"@D)=V%I=#L@+2T@=VEL
G;"!W86ET(&9O<F5V97(-"@E%3D0@4%)/0T534SL-"@T*14Y$.PT*
`
end


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