Serial I/O Question

"motty" schrieb im Newsbeitrag news: snipped-for-privacy@d34g2000cwd.googlegroups.com...

it depends, if the clock derived from 26MHz stays in 'fixed' phase align during each frame, then its easy. if not then it can be rather complex.

all you have todo is to have 4 phase captures per bit and choose the best - you can achive this by having 4 clock phases, as you are doing

or you can use 1 or 3 IDELAYs calibrated and adjusted to have samples at about the equal time slots to slice the input data properly.

its still bit tricky as you can only have one IDELAY per iob, so you need some trick, like 3 pins in parallel, well you have to experiment a bit, but this should defenetly be doable in LXxx -10 the 300mhz clock domain part sure needs special care.

but the Virtex-4 LUT and fabric is rather fast, I have measured in fabric actual clock rates up to 975MHz in slowest speed grade V-4 well 1GHz signals are not able to travel very long, but having small part of the design to run at 300MHz should not be rocket sience.

ah, the MGTs can of course also be used, I have made some test using V2Pro MGTs as super-sampler at 3GHz sampling rate but the logic to recover date from behind MGT used as shift register isnt so trivial either.

(not sure if SERDES was reference to MGTs or the V4 IDELAY/ILOGIC?)

Antti

Thanks Antti!

Unfortunately, the phase is not guarenteed over multiple frames. The interface needs to be able to sync each frame transmission. It's is definitely going to be tricky.

The SERDES I was referring to was in the ILOGIC stuff. I haven't even looked into using the MGT's, though that may be a possibility.

Oh well......

The method I'm using (derived before finding this XAPP) in the Spartan3E family has a phase locked clock and a long training period to recover 3 channels of 600 Mb/s data each. I don't believe (I'm not sure) the method in XAPP671 needs much of a training period. While the 300 MB/s is easily half the speed covered by that app note, you might find good ideas there. _____

MGTs on V4-LX parts? You may want to revisit the datasheet before getting your hopes up: only the FX V4 variant has MGTs. Unless you can still ECO the part and live with the price delta between the two parts, this avenue is busted.

Yeah, I am not well versed in the V4 parts, but I quickly found out the LX doesn't have MGT's. : )

We will eventually be using a V5 part, so I need to look into those details. I don't know if the MGT would work anyway. It lists a minimum frequency of ~600 Mbps. I don't know if that is a hard line or not. But right now I am just looking in to what methods are available and trying different approaches.

I tend to overlook that sort of details too when I am too busy with global aspects and have no immediate time to worry about specific (sub-)modular aspects.

As for the MGT's 622Mbps bottom limit, this is due to clock recovery delay lines - in order to keep the MGT macros' footprint down to reasonable levels, they have to keep the amount of delay taps in the CDR circuitry down. Xilinx probably chose this value because it covers the transition from the upper range of what is doable in user logic up to OC48 and beyond.

Since ASICs are always designed for worst-case timing to maximize yields (this is why a 600MHz design is tuned to pass 650+MHz gate-level timing simulations), MGTs can probably go at least 10% lower than that if you are willing to sacrifice process/environmental/etc. safety margins. Also, since this would be unqualified territory, you would be on your own as far as Xilinx is concerned.