Hi!
I need to design a simple serializer/deserializer as part of my bigger experimental project. I've started with reading various application notes from Lattice, Xilinx and Altera, as I don't feel very comfortable with multiple clock domain designs, nor with very high speed clocks in general.
I've found one slightly confusing sketch in Lattice app. note, available here
Figure 5 shows a basic serializer. My understanding:
- 'LS Clock' is derived by dividing HSTCLK by n, so both clocks are in phase
- 'Align' block is clocked with HSTCLK and it asserts 'Parallel Load' output for one HSTCLK period, when it detects rising edge of 'LS Clock'
- looking at serializer timing diagrams (p. 27) I can see that output (and thus parallel load) is delayed by 2 HSTCLK cycles, which confirms my understanding so far
Q: Given all that - why do we need 'Parallel Sync Register' ? Parallel load to Shift Register is delayed by 2 HSTCLK cycles from 'LS Clock' rising edge, so 'Parallel Load Register' outputs have enough time to settle.
Where is my misunderstanding?
Best Regards, Przemek