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Sensitive List Question

Hello

I have got a statemachine which is sensitive on current_state and a start Signal. Everything is working fine but when I synthesize my design the tool gives me a warning that signals in the sensitive list are missing. In detail it is a counter signal and a intern register of the state machine.

So my question is: Do I have to add these signals to my sensitive list, although if the change there has no effect at all? Or can I also leave them out and ignore this warning from the synthesizer?

Thanks James

Reply to
James
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Firstly its called a sensitivity list :) and secondly its really only used by simulators the synthesis tools don't actualy take any notice of what is and what isnt on the sensitivity list when synthesising logic.

Reply to
Jezwold

I should add that if you have simulated something with an item missing from the sensitivity list,then the reason you get a warning from the synthesis tool is that the behaviour of the synthesised logic may differ from what you simulated because sensitivity list items do have a profound effect on how your simulation will behave.

Reply to
Jezwold

"Jezwold" schrieb im Newsbeitrag news: snipped-for-privacy@c13g2000cwb.googlegroups.com...

in the end I should just add all my values to the sensitivity list, so that the synthese tool is happy?

Reply to
James

yes if you use modelsim you will find an option called synthesis check , or something like that which basically checks that all the items in a process that effect the logic flow have entries in the sensitivity list.

Reply to
Jezwold

Consider using synchronous processes.

-- Mike Treseler

Reply to
Mike Treseler

The reason being I belive that then you can just have the clock in the sensitivity list (and reset if asynch reset).

As long as all logic statements are wrapped in a "if (clk'event and clk=1)" then simulation and synthesis results (in terms of logic) should be the same and any "missing signals from sensitivity list" warnings can be safely ignored (as far as I am aware...)

Cheers,

Ken

Reply to
Ken

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