Hello,
I am in the midst of reviewing a board design, which is based upon a (Xilinx) Virtex-4 XC4VSX35 which will configure itself as a master from a (Xilinx) XCF32P flash.
The related schematics was heavily inspired by a reference design, which allows loading the configuration either in serial mode or SelectMap. A jumper changes the mode bits accordingly, so the FPGA knows what we want. In order to make this work, the ROM's D0 output goes both to FPGA's D_IN_0 and the D0 pin. D1-D7 go, of course, to the respective places on the FPGA. This way, both data channels are possible.
In our design, the mode bits are hardwired to SelectMap, so I have to make sure that things will work in this mode. And what puzzles me, is how the PROM knows whether it should send out a single bit for each CCLK as necessary in serial mode, as opposed to a full 8-bit word per CCLK as needed in SelectMap. The mode pins don't reach the PROM directly, and it has no way to know whether we're listening to one bit or eight. Still, it has to increment its bit address by one or eight, depending on the configuration mode.
It's not that I care all that much about the internals, as I want to make sure that we don't miss a critical wire or pullup/down resistor. Or something.
Does the FPGA send a hint regarding the mode in some way at powerup? Is it somehow given in the PROM data? I've read the configuration guides back and forth, and found no clue about this simple question.
Anyone?
Thanks, Eli