Hi, Within our ASIC library, we have an I/O pad which has input pins allowing us to select whether a pullup, pulldown or none is enabled for this pad. This is very useful for GPIO.
We are using an FPGA (Xilinx Spartan 3) as a delevlopment platform, and we would like the same functionality.
I think the OP was looking to change the pullup/pulldown/keeper dynamically. The IOB structure is programmed at config time. There is no "input pin" to the IOB selecting this feature unless I've missed something here?
I agree - as a seasoned Xilinx user, the complete user guide does little to suggest that there's pin-level control over I/O pullup/pulldon for such uses as GPIO.
Why bother with pull ups, pull downs on a bi-directional bus?
Doesn't such bus have signals that tell it when to "ignore" data?
On an input, why would you have to turn the pull ups on and off?
Having intermediate logic levels on an input pin is of no consequence to a FPGA device (we just design it so that there are no EM, SI, or other issues). Because an ASIC requires tricks to "prevent" intermediate voltages on pins is a fault of the ASIC cell performing that function, not a function we need to provide!
Designing for extremely low power, and requiring inputs to have no contention would be best done by always having an active CMOS driver to the pin (always): adding pullups and pull downs wastes power, too.
Why? .. so you don't have to have pullup/pulldown on the board. Also you may want to change between having a pullup or pulldown or none. Much easier to do by controlling the PAD rather than controlling additional circuitry on the board. Much less board space too.
For your prototype you might want to consider my favourite solution:
Use two I/O pins instead of one. Consider one of them as "data" pin and route it to your peripherial. Consider the other one as "pull" pin, and connect it with a 20K resistor to the data pin.
For "input", put both pins in tristate. For "pullup", put the data pin in tristate, and the pull pin in output-high (the peripherial sees
We are using an off the shelf development board. Although it has space for user functionality, this will be taken by our mixed signal test chip (to form the complete system).
Steven, obviously you can configure the part with either pull-up, or pull-down or neither on any individual pin. Austin showed you the drawing. Why are you ineterested in making these changes later on, in a working system? That's really the only thing that is complicated. So, why do you feel it is necessary? Peter Alfke
It appears the use is for GPIO controlled from embedded software which will be used in the ASIC.
Lost from the original post:
Hi, Within our ASIC library, we have an I/O pad which has input pins allowing us to select whether a pullup, pulldown or none is enabled for this pad. This is very useful for GPIO.
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here.
All logos and trade names are the property of their respective owners.