See Peter's High-Wire Act next Tuesday

Peter,

Thanks for the heads-up.

You'll do great. And remember, we'll all be sitting behind our monitors -- NAKED!!! Thinking about this fact should relieve any potential nervousness you will have.

Bob

Don't forget, it's tomorrow, Tuesday, at noon Pacific Time. Altera Marketing has e-mailed me and promised their attendance. I will not disappoint them. So join me tomorrow for some serious and fun talk on FPGA performance. Peter

my

act

Peter,

You were superb!

Those built-in async fifo controllers, in Virtex-4, are amazing. I wasn't aware that they were in there. It's a good thing that Xilinx had the foresight to hire that FIFO expert (whoever he might be).

;->

Bob

Thanks, "Bob". There was some confusion about the apparent or virtual delay between slides, and I should perhaps have talked more slowly. But totally I am happy. No responses yet (except yours), but perhaps later. The emotional words about benchmarks were no play-acting. I still have scars from Altera's reckless destruction of the old PREP cooperation, more than a dozen years ago. And they are still up to their same old trickery. Their newest game is giving leakage current values at 25 degrees. Nice numbers, but totally meaningless and utterly misleading. How does one expose this? Legally, it's not exactly a lie, but it has the same effect as if it were. Some engineers and managers may even be inexperienced enough to fall for this kind of nonsense. The question is just: How fast will it backfire? The earlier, the better ! No wonder smart engineers have developed a deep suspicion of marketing... Peter

...

Is the recording of the talk available on the net?

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

It was interesting to note that the slides seemed to appear on this side of the pacific, before you were able to see them ?

I did think (evil grin) of asking about "Why not use PREP for FPGA benchmarks ? "

... Wait for the app notes covering thermal runaway on FPGAs ?

-jg

I saw the material and Altera's story as well. Why is Altera talking these unknown design based benchmarks that deal only with the fabric ? I have had more problems meeting I/O bandwidth and timings for 266Mhz I/O designs than anything else.

Hi Che Fong,

Core logic/routing performance is only one aspect of the overall performance/design suitability question. Many customers *do* have trouble meeting timing in the core of their design, and a faster chip (e.g. Stratix II) can make it easier to do so, leaving you with more time/energy to spend on other problems such as I/O interfaces and debugging. A faster chip can also mean you can by a cheaper speed grade and still meet core timing, provided that device meets your other needs.

If you don't need core performance at all, then that particular aspect of Stratix II will not be of use to you. Everyone has different needs. Many customers do need speed.

Regards,

Paul Leventis Altera Corp.

Nice

one

is

Wow. I can't believe how completely backwards this is -- who is lying here Peter? Who is playing the "games"?

have provided static power as a function of junction temperature (ranging from 25C to 100C) and process (typical and worst-case silicon).

Contrast this to your Virtex-4 data. Until two weeks ago, the only available data was 25C, Typical silicon. Then with WPT 4.0 you finally caught up on temperature-dependent static power. But still, only typical silicon. Sub-threshold leakage increases exponentially with threshold voltage and gate length, and thus is extremely sensitive to process variation. I wonder how many of your customers have fallen for your marketing story only to find themselves with atypical units of silicon that burn more power than your spec?

Altera prides itself on operational excellence and reliability. This extends to our power models. At the introduction of Stratix II, we provided conservative power specs (both typical and worst-case) to ensure that our customers could safely design to this product. These specs reflected the uncertainty that comes hand-in-hand with software before silicon release. As the various family members have come back from the fab, we have tightened the specs based on preliminary measurements, and we will further improve things in the future once full data collection and analysis is complete.

Dare I point out that the copious amount of press release/collateral/FUD you guys have disseminated over the past year on power is based on "totally meaningless and utterly misleading" (your words) 25C typical data for Virtex-4?

You have no worst-case data and you do not have any real power tools for your Virtex-4 customers. I think you should be the one worried about backfire.

have

coo=ADperation,

I know nothing of PREP (before my time). But if you have specific concerns with the benchmarking methods we use, I'd love to hear them. There is no trickery -- Stratix II has a +39% performance advantage. Regards,

Paul Leventis Altera Corp.

other

aspect

needs.

I think these benchmark perforamance comparisons for the fabric are biased. Altera says Stratix II is 39% better than Virtex-4 Xilinx says Virtex-4 is 10 % better than Stratix-II I bet both companies biased their results. Who is to tell otherwise. Where are these designs ? Are they available to the public ? How much effort was really put into making them optimized for the other guy's device. C'mon, give me a break ! ;-) Enough of this chest punding BS !!!

Che

Hi Che Fong,

I can't speak for Xilinx, but we did not bias our results. If you look at our Stratix vs. Virtex II data, you'll notice we do not try to claim a large performance advantage, even though we could have if we chose to bias our data. Those families had similar performance. Stratix II improved on Stratix (somewhere in the vicinity of 45% better core performance) through a combination of process and architecture improvements. Virtex-4 has not -- we have benchmarked Virtex-4 vs. Virtex II-pro and found very little difference in performance. So have customers and posters on this bulletin board.

The lack of publicly available credible benchmark designs is unfortunate. It would help clear the waters in benchmarking, and it would also help academics who develop cad tools and new algorithms to apply them to real-world problems. We cannot release our benchmark circuits, since they were originally the IP of (real or potential) customers who provided us the design under NDA.

We made no effort to optimize the designs for our chips. Some of our designs were originally targetted at Xilinx chips, and all we do to these designs is replace DCMs with PLLs and replace any RAMs with lpm_ram.

I strongly encourage you to take your designs and try them out on Virtex-4 and Stratix II. You decide -- in the end benchmarks can only give you an indication of what to expect. Real performance depends on exactly what your design is and what resources it requires. Both Altera and Xilinx provide free place & route tools (see

so you can easily make your own head-to-head comparison.

For more details on how we benchmark, see

Regards,

Paul Leventis Altera Corp.

I seldom have serious issues with Paul (he is not part of their local marketing snakepit anyhow) and I will not have a dirty fight with him. Altera had skewed the benchmark results in their favor by comparing their fastest against our middle speed grade (I know that our fastest speedfiles were not yet public, but that is a poor excuse if you want to create benchmarks for the benefit of the public. Learn from tennis, where you don't surprise a temporarily not-yet-ready opponent !) Altera also did not use the Xilinx software the way a user interested in top performance would use it. And bingo: +39% ! No lies, just cheats. The stable of designs is naturally different in the two companies. And they are not public...

My intent was not to battle the 39% (that would have been a different presentation, and a different presenter). My intent was to convince you that such benchmarks, based on legacy designs are irrelevant, since the real performance criteria are elsewhere, namely in novel and innovative functionalty and systems features. Maybe I succeeded. ;-) Thanks to all who had the stamina to listen to the bad audio track. The accent is mine, but the fade-in and fade-out happened elsewhere. The mike was a constant 2 inches from my mouth... On the 15th, same time, we will cover power consumption in Virtex-4. Peter Alfke, Xilinx Applications

Sunds like Altera BS is bigger than Xilinx ! ;-)

Sunds like Altera BS is bigger than Xilinx ! ;-)

Sunds like Altera BS is bigger than Xilinx ! ;-)

Then you need another class of benchmarks, that ARE public ?

If you look at the EEBC (sp?) Embedded controll benchmarks, they also extend the meaning of benchmarks by having TWO columns.

a) = "out of the Box" = Std tools, Compilers, not hand level tuned in assembler, or using special HW fabric.

b)"Optimised" = Experienced designer, hand optimised Assembler,and using all relevant special HW fabric.

Not surprisingly, there can be 10:1 or 100:1 between a) and b)

So, how about making some PUBLIC simple candidate benchmarks ?

They need to be small enough to understand, but difficult enough to push the devices.

How about :

1) DDS Synthesis - 24/32/40/48 bits wide, and using a) fabric only, Most Portable HDL b) HDL, but using special HW support features c) [if applicable] full optimise, including hand placement [least portable]

2) Frequency & Period Counter : BCD and Binary alternate designs, 8-12 digits, Reciprocal counting, results to spec Fmax, dT min, and Digits/Sec of gate time.

3) PWM/Pulse generation - word widths as for DDS: Simplest form is gated counter, but FPGAs have many time-domain HW supports, that have higher resolution so the optimised form of this benchmark, would use any time-domain feature you like. Self-Calibrate is ok.

4)SoftCPUs : SoftCPUs are advancing, and there are public cores out there. This gets more political, as these make very good benchmarks, but IC vendors would much rather lock customers into their own SoftCPU, so do not want to publicise any alternatives.

etc

-jg

Jim Granville wrote: (snip about benchmarks and lies, not that benchmarks have ever done better than that. Remember MIPS...

Meaningless Indicator of Processor Speed.)

I thought about this some years ago, what is needed is a scalable benchmark that can adjust to the size of the FPGA. At the time I don't think it was very practical, but it might be better now. FPGAs are bigger, so the error due to requiring a whole number of units to fit is smaller.

One possibility could be an N bit processor where N is adjusted as appropriate. Another is N of your favorite vendor independent processor, the smaller the better. For each device N is adjusted to maximize the product of N and the speed, thus balancing routing effects. (If you pack too much in the routing can slow down the logic.)

Other scalable design ideas could be offered.

-- glen

I hope nobody wants to repeat the PREP experiment, killed -as most people would agree- by the devious tricks of a certain company, not dear to my heart. :-( But think for just a moment: Today, there really are only two serious contenders X and A. the rest are niche players, and getting smaller every year. Now imagine that there were a universal, scientific, believable, accurate set of benchmarks. I would hope that Xilinx wins, but that would be the end of Altera. The other way round, it would spell the end of Xilinx. Nobody really wants either of that to happen, least of all the users. They actually want biodiversity, for several good reasons. Competition sees to it that the two main players have comparable qualities, otherwise one of them goes down, and the other one goes up. The better one becomes or stays #1, the lesser one becomes or stays #2. That's the way Xilinx and Altera have ranked for many years. Altera has a stable %PLD market share in the lower 30s(now 34%), Xilinx moved up from the high 30s to now 52% PLD market share. That's the result of good products and happy customers, not of benchmarks! Capitalism has some advantages, you cannot fool the market in the long run.

The only people benefitting from benchmark wars are the marketing and sales departments of the two FPGA houses. For the rest of the community, it's a silly circus. Well, some people enjoy a bloody circus... Nero did. Peter Alfke

Certainly seems "benchmarks" should now include a date (and time!) - [Remember the days when you could just specify a Device family... :)]

I see Altera have just anounced updated Speed and Power Parameters too, on their devices.

Claims of +20% on Max speed, -45% on static Power, and no inrush...

Xilinx will, of course, include these 'still warm' numbers in their V4 Power comparisons comming soon...

-jg