Ok, I finally got ST2 going and it's great! But everytime a add or change a signal to look at it does a full rebuild (~20min.)
The docs seem to indicate that simply adding a node shouldn't take so long, but I can't figure out how to affect it. Smart compile and all the options listed in the docs are turned on, but I don't see any benefit.
Even if I just press the build > twice in a row without editting *anything* it still does a full build.
What's the secret? :)
Thanks, Ken
Hello Ken,
Here is the secret taken from the Quartus Documentation.
"Before using the SignalTap II incremental routing feature, you must perform a Smart compilation by turning on Automatically turn on Smart compilation, in the SignalTap II Logic Analyzer page of the Settings dialog box (Assignments menu). Also, you must reserve trigger and/or data nodes for SignalTap II incremental routing using the Trigger Nodes allocated and Data Nodes allocated boxes before compiling the design, and you must assign a SignalTap II incremental routing source by selecting SignalTap II: post-fitting in the Filter list in the Node Finder."
Hope this helps.
Subroto Datta Altera Corp.
change a
long,
options
*anything*Hello Subroto,
Thanks, I missed the part about manually over allocating Data and Trigger Nodes. I'll try that.
Also, do you just hit the normal "Start Compilation" button (>) or do you use incremental route or something. I tried Signal Probe Compilation under Processing->Start, but I haven't tried Incremental Fit.
Do you have any tips for either finding renamed (?) post-fit signals or a shure fire way to have a signal not optimized away? Inserting LCELL's (graphical) and naming both the input and the output. I've also got some AHDL and I haven't seen the equivalent of the Preserve or Keep directive. If you don't mind, could you or someone post a snippet of AHDL placing a signal into a named LCELL?
BTW, I'm loving this LA. This is like having a source code debugger for hardware! I've put my physical LA away for now as ST is much more flexible and trustworthy.
Ken
Hit the normal compilation button. Let the smart compile logic decide which compiler executables to call. SignalProbe is a different product and is used to route an internal node to a reserved pin. SignalProbe compilation is not applicble here. Incremental fit is an entirely different flow and is not applicable here.
See the code fragment below.
-- This design will generate 2 LEs after synthesis due to the LCELL buffer.
-- Without it, the compiler would choose to pack all the logic into one LE.
SUBDESIGN an_lcell ( a,b,c : INPUT; z : OUTPUT; )
VARIABLE my_specially_named_LE : lcell ; -- Will become the output of an LCELL BEGIN
my_specially_named_LE = a AND b;
z = my_specially_named_LE AND c;
END;
This type of code is only required when one wants to view an internal combinational signal, and we recommend that users first look at the contents of registers before resorting to this technique. Registers should never be optimized away and their names should be easy to find without using an LCELL buffer. If a register that the user wants to look at has been optimized away then this is an indication that there may be an error in the user's design, as synthesis will never optimize away a register that is necessary for ciruit function.
It is probably also worth pointing out that an LCELL buffer will not preserve a fanout-free signal.
Hope this helps
Subroto Datta Altera Corp.
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