Hello,
I am not sure if this is the right NG, but since it concerns memory driven by an FPGA, here goes.
My question is about burst writes to SDRAM memory (be it standard, DDR or DDR2).
Is it possible to sustain a burst write for an undefined number of words? Here is my setup: I have some incomming flow of data arriving at a constant speed of, say 250 MWords/s, which needs to be written to memory in a sequential order, until a Stop signal ends the burst. The length of the flow can be as long as several times the size of the memory, in that case the latter data overwrites the old one.
Do SDRAM require dedicated refresh cycles, even if the write cycles will access in turn every possible location in the memory?
Alternatively, would there be a way of refreshing a bank while writing into another one, without interrupting the 250 MWrd/s data flow?
If this is technically possible, do SDRAM Controller IPs available from FPGA vendors (i.e. Xilinx, Altera) support sustained writes with no gaps in data flow?
Any pointers to litterature, memory types, SDRAM controller IPs, would be appreciated.
Alex