SDRAM controller

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Hi all,

can anybody tell how autorefresh in SDRAM exactly works? suppose in
SDRAM specifications it is mentioned that 64 ms, 4096 cycle
refresh(15.6 us/row) what exactly it means and how we need to generate
the autorefresh cycles.

actually i am trying to upgrade the 512k*4*32 SDRAM(Fujitsu Make) to
Micron Make 1M*4*32 SDRAM.

FUJITSU specifies that 4K refresh cycles every 16ms, auto refresh (3.9
us) and micron specifies that 64 ms, 4096 cycle refresh(15.6 us/row).

Did any body tried to do this kind of upgradation. we have the CPLD
which controls the Fujitsu SDRAM  and other we want to
upgrade the SDRAM as i mentioned above.

Anybody can help in this regard please reply to .i can send u the data sheets of both the
SDRAMs,if you want.

thanks and regards,


Re: SDRAM controller
in general the 64mS says that you need to complete all the 4096 cycles in 64
mS period. how you do it it is your choice (based on the application) = you
can do 4096 refresh cycles in a clock by clock (NOT real-life option) and
after these 4096 clocks go to sleep or do your algorithm until the next 64mS
starts or (another scenario) you can do some N refresh cycles together and
repeat this so 4096/N such events will take less than 64mS, etc.
as the SDRAM takes care inside for the refresh it actauly means that you
will "visit" every SDRAM line in 64 mS and this will prevent the data from

as for the upgrade -->
the X mS period is the MIN. as you see Fujitsu asks for 16 mS while Micron
wants 64 mS = actualy you need to do NOTHINg as what will happen with the
Micron is that it will "over-" refreshed (x4) but this odes NOT make any
damage at all ! doing the oposite (Micron --> Fujitsu) will NOT work as than
if the design is for 64 mS and the device expects 16 mS the data might
disappear (might as if you still keep accessing the SDRAM it will take
longer time for this effect).

hope this helps.


                           yours -
                                     Arie Z.

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Re: SDRAM controller
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And one of the many advantages of an FPGA is that if you know
enough about the application to know that every row will be visited
anyway you don't need to refresh at all.

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