HI Everybody!
I'm having a timing problem interfacing with my SDRAM bank. I'm usin
256Mb MT48LC16M16 SDRAM from Micron, and want to operate them at 100 Mhz So far I have only been working at 40 Mhz.I'm using two DLLs (inside my VirtexII) one for clocking the FPGA and on for clocking the SDRAM. The design works if I DON'T use the externa feedback from SDRAM_Clk to one of the DLL, but it fails as soon as I us the feedback (Which according to Xilinx should be the correct way t terminate clock Skew).
The feedback to the other DLL is taken from clock output of it self, and have used IBUG/OBUF/BUFG so that is not the problem.
Hope some one can help me . Best regards, /P