SDRAM

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Hi all,

can anybody tell how autorefresh in SDRAM exactly works? suppose in
SDRAM specifications it is mentioned that 64 ms, 4096 cycle
refresh(15.6 us/row) what exactly it means and how we need to generate
the autorefresh cycles.

actually i am trying to upgrade the 512k*4*32 SDRAM(Fujitsu Make) to
Micron Make 1M*4*32 SDRAM.

FUJITSU specifies that 4K refresh cycles every 16ms, auto refresh (3.9
us) and micron specifies that 64 ms, 4096 cycle refresh(15.6 us/row).

Did any body tried to do this kind of upgradation. we have the code
for Fujitsu SDRAM specifications.

Anybody can help in this regard please reply to
snipped-for-privacy@myw.ltindia.com .i can send u the data sheets of both the
SDRAMs,if you want.

thanks and regards,

S.RANGA REDDY

Re: SDRAM
a
snipped-for-privacy@myw.ltindia.com (RANGA REDDY) wrote in message
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Re: SDRAM
I think, you just send auto refresh command to sdram, and set a count,
let it count down from the cycles it needs. When count equals 0, then
auto refresh is finished. SDRAM does the job automatically.


Steven



snipped-for-privacy@myw.ltindia.com (RANGA REDDY) wrote in message
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Re: SDRAM
Hi

is it true that Micron SDRAM does not require any refresh cycles if we
are reading the SDRAM rows once in 20 ms atleast? if i dont give any
refresh cycles what will be the condition of the SDRAM?

please reply me answer..

regards,

S.RANGA REDDY
 


snipped-for-privacy@lycos.de (Steven) wrote in message
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Re: SDRAM
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AFAIK, *no* SDRAM requires refresh cycles if all the rows you care about
are touched (read or written) sufficiently often.  I think once every
64ms is enough.

I've never seen anybody take advantage of that though.

Tommy


Re: SDRAM
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There are some apps where the refresh is done automatically by the
repetitive accesses, like video for example.  The refresh period varies
with different row/column sizes and layout, so check the data sheet!  I
recall that the older parts were in the low ms range, but the period
increased as the number of rows increased.  

--

Rick "rickman" Collins

snipped-for-privacy@XYarius.com
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Re: SDRAM
[DRAM refresh not needed if you read/write often enough]

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We built a delay line using DRAM.  The idea was to simulate
a 10,000 km 155 megabit link in order to test software.

No refresh needed.  Just assign the RAS/CAS bits such that
you use each row often enough.  On the other hand, you can
save power if you don't touch rows more often than necessary.

--
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
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Re: SDRAM
snipped-for-privacy@suespammers.org (Hal Murray) wrote in message
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Curious, I am planning on making my cpu DDR interface run as hot as
possible (not that I like heat) but I am running no sram data cache
since the ld/st address for 16 threads will be more random than a
small cache could handle.

The DDR specs I have from Micron are vague on power dissipation or I
haven't found it yet for the case I am interested in.

In order to allow so many threads I also need to thow them around to
different banks, if they all hog 1 bank, perf would be impacted.

So how much power can a typ 256M DDR DRAM dissipate when running
Ras/Cas cycles as often as possible at say 250MHz and on random banks
1 or 2 simultaneous?

regards

johnjakson_usa_com

Re: SDRAM
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There is probably a section on current used under various
conditions.

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Re: SDRAM

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Our video-processing app doesn't bother with refresh for the display
frame buffer.

Cheers,
Martin

--
snipped-for-privacy@trw.com
TRW Conekt, Solihull, UK
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Re: SDRAM
A read on a row in SDRAM accomplishes a refresh, so if you read all used
rows within the refresh period, you do not need an explicit refresh.  I've
used that in video applications on several occasions.

Tommy Thorn wrote:

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--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
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Re: SDRAM
snipped-for-privacy@yahoo.com says...
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The original IBM PC had one of the DMA channels set up to do periodic
reads from contiguous locations to the DRAM refresh.

--
  Keith  

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