What does SDF, and Back-annotation/Forward annotation mean? How is an SDF File generated and by which tool?
Can someone explain how to do synthesis and what tools/file extensions (.sdf, .lib etc) mean?
What does SDF, and Back-annotation/Forward annotation mean? How is an SDF File generated and by which tool?
Can someone explain how to do synthesis and what tools/file extensions (.sdf, .lib etc) mean?
The Standard Delay Format (SDF) file stores the timing data generated by. EDA tools for use at any stage in the design process.
SDF can be generated by most ASIC synthesis, P&R or STA tools. Accuracy will vary though depending upon which stage in the design process you are).
As to how to perform synthesis, read the user guide for your synthesis tool.
Cheers, Jon
process.www.eda-stds.org/sdf/sdf_3.0.pdf
Thank you Jon.
So my understanding is that
RTL Code + synopys Design Constraint (.sdc) files are fed into synthesis tool, it generates a .v / .vg netlist file plus the .sdf file. Correct?
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.