Schematic Entry, Xilinx or Altera?

Altera

Regards,

Thomas

Altera Quartus.

-- Mike Treseler

Parkov,

I would invest my time in learning a HDL: VHDL or Verilog.

Schematic entry for logic design is (almost) completely dead. It has become rare to find anyone doing anything in schematic form, except for the highest level where the pins are connected.

All of the levels of logic are described in hardware design language (HDL) modules.

To pick a vendor based on their 'schematic tool' is probably the least interesting criteria.

Picking the vendor based on:

-available technology

-speed

-power

-features

-cost

-size

-package

-ease of use of software tools

-available synthesis tools

-available simulators

-FAE support

-web support

-part availability

all makes sense.

Austin

Good advice, but allow several months.

The one place it isn't dead is for circuit-board oriented, first-time cpld users copying some glue logic off of an application note.

-- Mike Treseler

Thats about where I'm at. No worries, I'm checking out the two HDL variants, just wanted to get a couple things rolling fast in the meantime. I'm coming from a 74xxx chip to chip background so I already have some designs on paper. Thanks for the heads up everyone on the Quartus recomendation.

But schematic entry oftem leads to non-registered designs, where you should allow several month of debugging too...

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Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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And be sure to try out the 7400 series library that is provided with Quartus too, to make your transition easier. Once you have your design working use the Quartus builtin Verilog or VHDL synthesizer to expand your knowledge of FPGA design.

Quartus allows mixed mode designs so that you can create design blocks as a schematic or HDL.

Hope this helps, Subroto Datta Altera Corp.

I was playing the OP's advocate here, because I started out where he is now.

Certainly HDL is the clean way to go. But I also know that many hardware guys will try it the "quick" way first.

-- Mike Treseler

There is also a 'middle ground', between VHDL and Schematics :

Use a Boolean Eqn language, such as

Xilinx have ABEL ( but for CPLD only, which here is OK ), Altera have AHDL ( I think still alive for CPLD ? ) Atmel have WinCUPL for CPLD, includes functional simulation, so can create test vectors, to allow 100% chip functional test at PGM time. This flow works best on smaller PLDs that are pgmd off-board.

Lattice also have ABEL, not sure on their plans for ABEL-MachXO support ? There is a large installed base of ABEL/Boolean EQN code for CPLDs, so if they want to migrate those designs to MachXO, that would be an important flow.

ICT have WinPLACE

If you start to need timing simulation, then you need to align to the simulation tools.

What complexity/package of CPLD do you expect to use ?

-jg

Hi Jim.

As far as I can forsee, all that I would need are either Altera EPM3032A/3064A's or Xilinx's XC9536/XC9576 both in 44pin packages.

If I went into a Boolean Equation Language, is ABEL or AHDL easier to learn/use? I can't seem to find any head to head comparisons. Is Xilinx going to continue support for ABEL for their CPLD's and is Altera going to continue support for AHDL for theirs? I know that these are not practical languages for complex FPGA design, but that doesn't need to be the issue. Tks.

Atmel's ATF1502 / 1504 would also be in that category. ( as would Lattice MACH4000 series ) Why not also the Coolrunner ?

Good questions, someone in Xilinx / Altera / Lattice could answer that ?

I do know from a 'tough' Xilinx.ABEL user, that Xilinx improved their ABEL flows, for CPLDs in recent releases - In their ABEL flow they now use (IIRC) VHDL as the 'back end' and ABEL as the front end.

This allows them to hook-into timing simulation tools, but does loose ABEL's test vector generation ? (useful only on smaller packages)

One they have that, of course, then 'continued support' is inherent, as the ABEL is only a front end.

That can't have been trivial to do, so I was impressed - but it does indicate how much CPLD code is out there, in ABEL/Boolean EQN.

In a similar vein, of using HDL's as 'back ends languages', see Jan Decaluwe's posting today of MyHDL : Python -> Verilog.

-jg

Further to this, I went to the Lattice web site

It says "ispLEVER-Starter Primary Module (212 MB) This module is required to run the ispLEVER Starter software, and should be installed first. It includes the ispLEVER Project Navigator, and all the tools and device libraries you need to implement a design in Lattice's newest and most popular CPLD products. Note: This module supports ABEL, EDIF and Schematic design projects only. For Verilog or VHDL design project support, you must download one of the Synthesis modules listed below." ...

Device Support

FPGA: LatticeECP: ECP6 LatticeEC: All LatticeXP: XP3, XP6

CPLD: MachXO: All ispMACH 4000 ispXPLD 5000MX

So, since MachXO is clearly in the "newest and most popular CPLD products" category, this web page is saying ABEL support for MachXO is there.

Call me cynical, but I'd believe that more if a Lattice FAE was able to verify that ?

-jg

And frequent use. It isn't worth learning either one for a one-time deal. If he only does a CPLD once in a blue moon and doesn't use the HDL for anything else, he'll forget more than he remembers and will have to learn it all over again next time.

I can't quite figure out what that means.

It sounds like forgetting to put in FFs to hold the data. But why does that happen more often with schematics than when using a HDL?

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In the current release (ispLEVER v5.1) the MachXO device family does require a Verilog HDL or VHDL synthesis front-end like Precision RTL or Synplify. You can use the schematic editor, however, there's currently no library for gate-level design so it's best used as a block-diagram editor. In the design flow the schematic editor produces a structural model that's read by logic synthesis. I use it today with the latest FPGA families (including XO):to organize RTL modules or those modules generated from IPexpress the module/IP core manager.

Meanwhile another option for someone who's trying to migrate a

74xx-class design is a 3rd party EDA schematic front-end like Aldec, Altium (Protel), or Orcad which can also generate EDIF 2 0 0 or structural HDL you can import into FPGA tools. Altium in particular is focused on making this "board-level" design style easy.

Troy Scott Lattice Semiconductor TME

Definitely Altera.

Thanks Troy - you might get them to change the WEB page, so someone who takes what it says, at face value, is not misled.

i.e. make it clear that whilst MachXO is called a CPLD for sales, from a TOOL chain viewpoint, it is a FPGA : Presently, ABEL flow _excludes_ MachXO, but includes all "product term" CPLDs

Do you know if Lattice plan to support ABEL flows for MachXO, to better tap into the CPLD user base ?

-jg

Why? Logic is logic. We do lots of complex designs, state machines and all, in schematic form, and they come up in days or hours.

John

If you do registered designs and don't relay on some function having some definite delay, things will be fine. However many TTL designs are created different...

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------