I saw this and thought of comp.arch.fpga . I'm not endorsing this, just a 'FYI'. I wonder if any of you guys have used this yet? I see it uses the X2Y caps we mentioned a few months back.
Anyway, I hope it's interesting. Cheers, Syms.
That looks really interesting. It mentions Virtex 4, and I'm guessing there aren't too mane versions of the PowerPoser available yet. I read in the Virtex 5 literature that the new devices have some bypass caps built into the package. I wonder if the PowerPoser would have as dramatic an effect on V5 signal integrity?
Regards, Gabor
Hi Gabor, Reading through the bumf on the Samtec site, it would seem that Virtex 4 onwards has built in "IC power rails with substantial in package and/or on-die storage".
Check out page 22 of this:-
I reckon it won't be long before the FPGA manufacturers will build the power poser stuff onto the part, but this looks like a good solution for now.
Cheers, Syms.
Hi Pete, I agree. I believe the V4 on-package capacitance is mounted on the BGA 'circuit board'. Somewhere underneath that metal lid. Cheers, Syms.
The only problem there is that it's difficult to get the capacitance values necessary for proper decoupling inside the silicon, but it's certainly going to significantly reduce ground/Vdd bounce simply because they [caps] are closer (in the inductive sense) to the load when within the package, and that's a limiting factor in many newer board designs.
This will make the designer's life simpler, but I suspect the only real 'tuning' is optimal part placement on the powerposer of the decoupling components relative to the targeted part power / ground rails.
Cheers
PeteS
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