safety critical applications with FPGAs/CPLDs

Falk

I have done three SIL4 fpga development on my last contract, we did not use certified tools as I am not aware there are any however we used very stringent RTL design guidelines, independantly developed test benches for each module which must achieve 100 % in code coverage for path, branch, statement, toggle, and condition at all levels. along with independant reviews of rtl code and module specifications / test specifications. Further more we used two synthesis tools targeting different technologies i.e. xilinx and actel and then used formal equivelence checking to ensure that the RTL against the implementation actel devices (the devices used were actel) were the same with no mismatches and then compared the xilinx against actel top ensure the synthesis tools had not filled any holes with logic. There are a few guidelines for coding RTL style to ensure all possible failure conditions are detecteable, I would be happy to advise you further if you would like to know more ? I think i have some documents I wrote on saftey critcal fpga design somewhere.

What is your intended application ?

hope this helps

Adam

"Ad" schrieb im Newsbeitrag news: snipped-for-privacy@i39g2000cwa.googlegroups.com...

Thanks for your reply! It gives a good first impression. Our application is a simple fall back braking system in a railway application.

I am very interested in further advices. One special question: Do manufacturers give any reliability data on how reliable the program is stored in Flash (CPLD/external in case of FPGA)? Might this reliability be sufficient for SIL2 or do I have to do certain checks on the "program data" of the FPGA/CPLD?

Falk

Falk

I have sent you a message to your personal email let me know if you do not get it

regards

Ad