Rumor Control:: Will Quartus phase out supporting AHDL?

Hi Joe,

AHDL support will be there in Quartus for a long long time.The AHDL language, is fully maintained and supported for reasons of backwards compatibility. There are lots of legacy Max+Plus II designs which customers are migrating to Quartus for use in both existing and new projects. We are sensitive to our customers needs and will not do anything to jeopardize their productivity.

Hope this helps, Subroto Datta Altera Corp.

I can see that they would move AHDL to "maintenance mode", but I doubt they would kill it entirely.

Altera took some trouble to keep the MAX +II interface option, and CPLDs must still be a sizeable chunk of their business.

I liked what Xilinx did with ABEL : that now generates VHDL output (IIRC), and so can hook into all the back end tools, whilst at the same time, preserve customers code base. In this form, ABEL is a valid choice for new designs ( esp in the CPLD arena ).

Altera could do the same, with their AHDL (or may have already).

Someone at Altera may clarify this ?

-jg

I find it interesting that Xilinx webpack has tools to convert AHDL to VHDL, but Altera does not! Of course, the copyright notice included in the generated code restricts its use to Xilinx products.

Andy

Jim Granville wrote:

Yes. In fact Quartus synthesis still maps a few VHDL code templates to .tdf (AHDL) blocks.

Still some reptile brain inside :)

-- Mike Treseler

Given Subroto's reply, why would Altera need to do this ? AHDL works fine, and is supported.

Xilinx, on the other hand, have to oil the pathways for Altera users, so they have to offer something...

-jg

Subroto Datta napisa³/a:

Is backward compatibility the only reason why Altera keeps AHDL in Quartus? Which languages Altera suggests to use in new projects?

czerstwy

You would never want to start a new project in an obsolete language like AHDL or ABEL. Verilog and VHDL are the only reasonable choices for new designs, personally I use Verilog but I don't want to start a religious war so lets just say both of those languages are industry standards and that code written in either can be easily ported to anybody's FPGA or ASIC.

I would suggest VHDL as a replacement for AHDL as the two are similar. Simon

ASIC.

Hello, both VHDL and Verilog are well established standards that have been widely adopted by the engineering community. Excellent behavioral simulators are available for both of the languages. Therefore it would be prgamatic to use Verilog and VHDL for new projects. AHDL is simple to use but a lot of what can be done in AHDL can be accomplished with Verilog and VHDL. As language parsing and synthesis are two separate processing steps all three languages benefit from the improvements that are made to the Quartus core logic synthesis and technology mapping algorithms. Therefore you will be able to achieve equivalent Quality of Results with all three languages.

- Subroto Datta Altera Corp.

I can think of several reasons Altera's own customers would want to do this, and that should mean that Altera should want to too.

For enterprises that have standardized on vhdl/verilog design methodology, yet have legacy AHDL code for which they don't want to throw away and completely start over. Granted, the resulting code is not always the best/most readable, but at least it works, and can be simulated right along side revised vhdl code to determine sameness.

For use with better synthesis engines (i.e. Synplicity), even for Altera targets.

For co-simulation at the rtl level with other vhdl/verilog simulators.

"AHDL works fine, and is supported" on Altera tools only. 3rd party simulation, synthesis and formal analysis tools are not supported, and won't be because AHDL is not a standard for anyone but Altera.

Andy

Jim Granville wrote:

I've assumed Altera allows mixed-source projects : so you do not have to re-code the AHDL much at all. Someone in Altera can correct that, if I am wrong ?

Of course, new projects should always have a language review, to choose the best tools to get the job done.

-jg

Jim, you are correct. With Quartus you can mix AHDL, VHDL, Verilog and schematics (bdf's) in the same project. As was pointed out earlier, if you are doing a functional simulation prior to place and route, or a timing simulation after place and route you will be able to use a VHDL or Verilog simulator, even if the sources are of different types. Quartus writes out a VHDL or Verilog netlist for the project in both cases. The thing that you cannot do in the mixed language with AHDL case is behavioral simulation prior to place and route.

- Subroto Datta Altera Corp.

Most projects I've been on that used legacy code still had to modify the code somewhat to suit the new use. Modifying legacy code in AHDL is not a good solution for us, since the reviewers are not AHDL literate (not that its that hard to understand), and it cannot be simulated on 3rd party simulators, except at the gate level, which is painfully slow.

I don't see where Altera would lose customers if they had the capability to convert AHDL to VHDL/verilog. They could put the same type of copyright restrictions in the code that Xilinx does if they wish.

Andy

Jim Granville wrote: