rules to assign pins to FPGA?

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I am a newbie and I need rules to assign pins to FPGA. I would imagine some,

1. Group signals that are natually related, and assign them to the same I/O
bank/side of the FPGA;
2. Let the software to assign pins, then fix some pins according to the
automatic assignment, then let the software run again. Do this iteratively
for several times.

What is your experience? Suggestions are welcomed.

vax, 9000



Re: rules to assign pins to FPGA?
Hi,

My recent experience is with Altera Cyclone

I needed to lay out the PCB first, so this is how I did it :

1 - Best possible layout for power supply pins and decouplers
2 - Best layout for clock inputs
3 - Dedicated functions (config etc)
4 - Use the general I/O in a way that gives the best layout (shortest
routes, fewest crossovers etc) - This will naturally tend to group stuff
functionally
5 - Tell Quartus exactly what pin-out I want

I have had no problems meeting my timing requirements (300MHz) and fitting
my functions with this device and this approach.

I remember a few years ago, old Xilinx XC5200 series devices were less
forgiving about this.

I'm sure this approach doesn't squeeze the last drop out of the device, but
the PCB sure looks beautiful

Gary

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Re: rules to assign pins to FPGA?

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some,
I/O
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This is the way to go. You need to watch out for SSO though.


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No, do not do this.

Jim



Re: rules to assign pins to FPGA?
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I agree about not iterating.

However, running a single unconstrained
place and route tells me
if the design fits at all, _before_
I manually enter lots of pin numbers.

It also gives me hints of router
preferences for pin assignments I don't
care about.


        -- Mike Treseler

Re: rules to assign pins to FPGA?
Vax,

DesignF/X(TM) - is specifically designed for this task and delivers
easy, rapid and accurate **Xilinx** FPGA pin assignment. DesignF/X
capabilites include:

1) Extensive DRCs that include all published rules related to pin
assignment.
2) Focus-filters that ensure only compatible pins can be assigned into
banks - for both single ended and differential signals.
3) Clock/data pin sync to enable rapid local and global clock driven
systems implementations.
4) Weighted Average SSO (WASSO) calculations that provide an essential
SSO check.
5) A comprehensive but easy-to-use GUI that supports rapid feedback,
problem resolution and task completion to make DesignF/X the easiest,
fastest and most accurate method of Xilinx FPGA pin assignment
available today.

We invite you to join several other FPGA designers and find out more
for yourself with our free trial download at http://www.prodacc.com

With best wishes,

Manu Pillai

vax, 9000 wrote:
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imagine some,
same I/O
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the
iteratively


Re: rules to assign pins to FPGA?
Thank you guys for the answers. I took Gary's approach to emphasize on PCB
layout first and still all the timing were met.

vax, 9000

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