Hello, all:
When I did the implementation of my design, the map process gave me the following error:
--------------------------------------------------------------------------------------------------------- ERROR:PhysDesignRules:1577 - Illegal routing. The DCM_ADV block has CLK output pin with incomplete or incorrect connectivity. Routing from the pin to a BUFG, BUFGCTRL or PLL_ADV block type was not found. The DCM_ADV CLK output pins can only route to BUFG, BUFGCTRL or PLL_ADV block types.
---------------------------------------------------------------------------------------------------- But I do have the CLK0 port connected with a global buffer : CLK0_BUFG_INST as shown in the following code. Can somebody tell me what's wrong here? I have spent a lot of time on it but still no clue.
Thank you very mucy, Rebecca
library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL;
entity dcm3 is port ( CLKIN_IN : in std_logic; RST_IN : in std_logic; CLKFX_OUT : out std_logic; CLK0_OUT : out std_logic; LOCKED_OUT : out std_logic); end dcm3;
architecture BEHAVIORAL of dcm3 is signal CLKFB_IN : std_logic; signal CLK0_BUF, CLKFX_BUF, Locked_out_buf : std_logic; signal GND1 : std_logic_vector (6 downto 0); signal GND2 : std_logic_vector (15 downto 0); signal GND3 : std_logic;
begin GND1(6 downto 0) CLKFB_IN);
Locked_BUFG_INST : BUFG port map (I=>LOCKED_OUT_Buf, O=>LOCKED_OUT);
DCM_ADV_INST : DCM_ADV generic map( CLK_FEEDBACK => "1X", CLKDV_DIVIDE => 2.0, CLKFX_DIVIDE => 5, CLKFX_MULTIPLY => 3, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 10.0, CLKOUT_PHASE_SHIFT => "NONE", DCM_AUTOCALIBRATION => TRUE, DCM_PERFORMANCE_MODE => "MAX_SPEED", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, FACTORY_JF => x"F0F0", PHASE_SHIFT => 0, STARTUP_WAIT => FALSE) port map (CLKFB=>CLKFB_IN, CLKIN=>CLKIN_IN, DADDR(6 downto 0)=>GND1(6 downto 0), DCLK=>GND3, DEN=>GND3, DI(15 downto 0)=>GND2(15 downto 0), DWE=>GND3, PSCLK=>GND3, PSEN=>GND3, PSINCDEC=>GND3, RST=>'0', CLKDV=>open, CLKFX=>CLKFX_BUF, CLKFX180=>open, CLK0=>CLK0_BUF, CLK2X=>open, CLK2X180=>open, CLK90=>open, CLK180=>open, CLK270=>open, DO=>open, DRDY=>open, LOCKED=>LOCKED_OUT_Buf, PSDONE=>open);
end BEHAVIORAL;