Hello all, I am doing a design with block RAM. The register block is part of the full design which is causing concern. The block diagram of the register block is at the link
- posted
17 years ago
Hello all, I am doing a design with block RAM. The register block is part of the full design which is causing concern. The block diagram of the register block is at the link
Also will there be any improvement in not specifying the global constrain like setting period for the 4x clock and instead specifying the needed constrain that is only the from to constarin for the blocks i have indicated in the block diagram
Since you're using a DCM, you don't need to put a period constraint on clk4x. You only need to specify the period on the clkin to the DCM and the tool will automatically propagate this constraints to the DCM outputs with correct phase adjustments. This of course requires you set up the DCM attributes correctly.
You can run the timing analyzer to see why you got a very high timing score and fix code and/or constraints accordingly.
HTH, Jim
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