Routing PLL output

Some additional thing:

"Differential" is the wrong expression. I need inverted clocks on a 3,3V logic level.

But in my opinion there is no 180° phase allignment given when inverting one of the clocks, isn't there?

Does QuartusII provide some module to make this phase allignment?

Thank you.

Rgds André

Hi Andre,

Just set the I/O type of the clock signal to be LVDS or another differential spec. It'll become differential automagically. With the appropriate electrical specs, of course.

Best regards,

Ben

Hi Andre,

Ooops... that complicates things a bit, since LVDS is only 2.5V in a Cyclone, and probably not enough voltage swing as well.

I suggest that you use normal I/O pins to generate the clock, or maybe use some external device to make sure that the LVDS I/Os are brought to a level that is acceptable for the recipient.

What was your base frequency again, and what is the output frequency?

Best regards,

Ben

Hi Andre,

You could use the c0 & c1 output of the PLL's, where you give the c1 an 180 deg shift, and both route them to output pins. The internal routing within the device and the placement of the pins could give some phase shift, but you could 'fiddle' around with that a little to get it working.

Karl.

Hi Ben,

thank you for your answer.

The base frequency that is the input of my PLL is 30MHz, the output clock frequency is 90MHz.

Rgds André

Hi Karl,

thank you for your answer. The problem is that c0 is a clock with a different frequency used for internal operations. That is c1 remains the only clock. So I could route this one to an output pin. But I also need an inverted clock of c1 to route to an output pin. So the only possibility would be to invert c1. But could that be a problem ? I mean the inverted clock then would not directly come out of the PLL ...

Rgds André

Hi Andre,

internal

output

If you do not make use of the differential output standard to generate the clock and !clock signals, nor use the PLL to do so, then you will have some delay of one clock relative to the other unless you are really careful. You could, for example, take your c1 clock and feed it to two parallel logic elements, which then take identical routes to two I/Os. One logic element does nothing (implements a wire function :-)), the other implements an invert function. If you place this LAB adjacent to the horizontal I/O that you want to bring the two signals out of, then you should get pretty similar, short routes from the LEs to the I/Os.

Do you need a known phase relationship between the internal clock and the external clocks?

Paul Leventis Altera Corp.

Hi Paul,

thank you for your help. What kind of logic element are you thinking of when you talk of wire function?

The phase relationship between the internal clock and the external clocks do not matter so that would be no problem ...

Rgds André

Hi Andre,

Actually, you don't need LEs at all. Just feed the output of the PLL and the negation of it directly to two I/O pins. The negation will be performed in the I/O interface. Be sure to place them in the same row/column on the same side to minimize skew. If you do so, the only difference in delay will be due to slightly different delays through the inverting and non-inverting paths of the I/O programmable invert. Oh yeah -- you should also make sure you use I/Os that have the same functionality. Any I/O that has dual-purpose will have slightly higher pin cap and thus slightly greater delay.

For example, in a 1C12 I used two I/Os in fourth row on the left side, and Quartus tells me I get 2.037 ns of Tco to each (from the PLL -> pin).

thepll mypll( // instantiates a PLL I made with the megafunction wizard .inclk0(in_clock), .c0(internal_clock) ); assign out_clock = internal_clock; assign out_clock_bar = !internal_clock;

In the event that you did want to use two LEs (as I suggested originally for some bone-headed reason), you can explicitly force Quartus to do so by instantiating an LCELL buffer. This example gives me something in the range of 2.7 ns of Tco. Not that the Tco matters.

thepll mypll( .inclk0(in_clock), .c0(internal_clock) ); lcell lcell1( .in(internal_clock), .out(out_clock) ); lcell lcell2( .in(!internal_clock), .out(out_clock_bar) );

You will also need to constrain these two LCELLs to be in the same lab near the I/Os you are driving.

Hopefully I didn't get too much of this wrong; I do not use Quartus much myself. This example and the add/sub Cyclone question were my first two verilog designs :-)

Paul Leventis Altera Corp.