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Rom Inference

Hi all,

I am using Synplify Pro for synthesis. My target FPGA is APEX20KE. I have the following code for rom but the attribute rom_style is not working instead it gave me the following warnings.

1) CL159 Input addrs_in is unused 2) Signal sincos_rom is undriven

entity Lookup is port( Addrs_In : in signed(ROM_DEPTH-3 downto 0); -- 10 bit Data_Out : out signed(ROM_WIDTH-1 downto 0) -- 16 bit ); end entity Lookup;

architecture Lookup_Synth_Arch of Lookup is -- Declaration for Rom type type Sincos_Rom_Type is array (0 to 2**(ROM_DEPTH-2) -1) of WORD; signal Sincos_Rom: SinCos_Rom_Type;

-- Attributes to map Rom to availbale techology library attribute syn_romstyle : string; attribute syn_romstyle of Sincos_Rom : signal is "block_rom";

begin

Data_Out

Reply to
Mohammed A Khader
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You sure you define your address as SIGNED ??? Your array is defined as natural range. It's also asynchronous. Maybe a clocked process ? did you simulate ? Where is it initialized ?

Synplify does usually a good job at inferring roms. Sometimes, some synthesis tools may decide that your rom contents make it easy to implement as LUTs.

I would try a synchronous Rom with initialized contents, declared as a constant (not signal) and unsigned index. I think Synplify does support ieee.math_real for constants so if you're going for a sine table, it's easy.

Bert Cuzeau

Reply to
Bert Cuzeau

Reply to
Ken McElvain

Hi Bert,

I have also synthezied with unsigned but the same error persist.

Its a part of a design , so I have to add some more logic after the Rom Output. I have used a different architecture for simulation which does the initialization of ROM from a file but rest is same. Yes, I have simulated and it worked. But after learning the APEX20KE ESBs I am thinking to add a register at Rom Output(to make it synchronus) and make some changes to compensate for extra cycle.

I cannot initialize the ROM in a case statement with 1024 of words(tooooooo Laborious).Is there any other way to do it . I thought attribute syn_romstyle(From synplicity ) would help me in recognizing so that I could initialize the ROM Later while programming the FPGA. How do you do for such cases.

Thanks a lot.

-- Mohammed A Khader.

Reply to
Mohammed A Khader

Hi ken,

Rom is having 1k of 16bit words. Hence I could'nt initialize it in a case statement. I thought attirbute syn_romstyle would help me in this . Is there any other way to do it .

Thanks .

-- Mohammed A Khader.

Reply to
Mohammed A Khader

You can define a constant array of integers (even put it in a separate package) for the rom contents. You'll need to also have functions to convert the array of integers into the init generics and attributes for the BRAMs. The advantage of doing it this way is that it is relatively easy to handle data that is bit sliced over several BRAMs (the init value function can take care of this) using plain text data. The integer array constant can be easily copied from Excel or Matlab and pasted into the constant declaration.

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--Ray Andraka, P.E.
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Reply to
Ray Andraka

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