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Rom Implementation in a CPLD

Hallo, reading XST user guide it seems that it's not possbile to implement a rom into a cpld, so I have made some experiment with the following code and ISE has compiled everything without reporting errors.

I don't have a real cpld to program, so I would ask if it can function before buying it.

type rom_type is array (359 downto 0) of std_logic_vector (15 downto

0); signal ROM : rom_type:= ( X"200A", X"0300", X"8101", X"4000", X"8601", X"233A", X"0300", X"8602", X"2310", X"203B", X"8300", X"4002", X"8201", X"0500", X"4001", X"2500", X"0340", X"0241", X"4002", X"8300", X"8201", X"0500", X"8101", X"0602", X"4003", X"241E", X"0301", X"0102", X"2122", X"2021", X"0301", X"0102", X"2222", X"4001", X"0342", X"232B", X"0900", X"0302", X"0102", X"4002", X"0900", X"8201", X"2023", X"0303", X"2433", X"0301", X"4004", X"0301", X"1002", X"2137", X"2036", X"0301", X"0102", X"2237", X"4004", X"0304", X"4040", X"2500", X"2500", X"2500",

X"200A", X"0300", X"8101", X"4000", X"8601", X"233A", X"0300", X"8602", X"2310", X"203B", X"8300", X"4002", X"8201", X"0500", X"4001", X"2500", X"0340", X"0241", X"4002", X"8300", X"8201", X"0500", X"8101", X"0602", X"4003", X"241E", X"0301", X"0102", X"2122", X"2021", X"0301", X"0102", X"2222", X"4001", X"0342", X"232B", X"0900", X"0302", X"0102", X"4002", X"0900", X"8201", X"2023", X"0303", X"2433", X"0301", X"4004", X"0301", X"1002", X"2137", X"2036", X"0301", X"0102", X"2237", X"4004", X"0304", X"4040", X"2500", X"2500", X"2500",

X"200A", X"0300", X"8101", X"4000", X"8601", X"233A", X"0300", X"8602", X"2310", X"203B", X"8300", X"4002", X"8201", X"0500", X"4001", X"2500", X"0340", X"0241", X"4002", X"8300", X"8201", X"0500", X"8101", X"0602", X"4003", X"241E", X"0301", X"0102", X"2122", X"2021", X"0301", X"0102", X"2222", X"4001", X"0342", X"232B", X"0900", X"0302", X"0102", X"4002", X"0900", X"8201", X"2023", X"0303", X"2433", X"0301", X"4004", X"0301", X"1002", X"2137", X"2036", X"0301", X"0102", X"2237", X"4004", X"0304", X"4040", X"2500", X"2500", X"2500",

X"200A", X"0300", X"8101", X"4000", X"8601", X"233A", X"0300", X"8602", X"2310", X"203B", X"8300", X"4002", X"8201", X"0500", X"4001", X"2500", X"0340", X"0241", X"4002", X"8300", X"8201", X"0500", X"8101", X"0602", X"4003", X"241E", X"0301", X"0102", X"2122", X"2021", X"0301", X"0102", X"2222", X"4001", X"0342", X"232B", X"0900", X"0302", X"0102", X"4002", X"0900", X"8201", X"2023", X"0303", X"2433", X"0301", X"4004", X"0301", X"1002", X"2137", X"2036", X"0301", X"0102", X"2237", X"4004", X"0304", X"4040", X"2500", X"2500", X"2500",

X"200A", X"0300", X"8101", X"4000", X"8601", X"233A", X"0300", X"8602", X"2310", X"203B", X"8300", X"4002", X"8201", X"0500", X"4001", X"2500", X"0340", X"0241", X"4002", X"8300", X"8201", X"0500", X"8101", X"0602", X"4003", X"241E", X"0301", X"0102", X"2122", X"2021", X"0301", X"0102", X"2222", X"4001", X"0342", X"232B", X"0900", X"0302", X"0102", X"4002", X"0900", X"8201", X"2023", X"0303", X"2433", X"0301", X"4004", X"0301", X"1002", X"2137", X"2036", X"0301", X"0102", X"2237", X"4004", X"0304", X"4040", X"2500", X"2500", X"2500",

X"200A", X"0300", X"8101", X"4000", X"8601", X"233A", X"0300", X"8602", X"2310", X"203B", X"8300", X"4002", X"8201", X"0500", X"4001", X"2500", X"0340", X"0241", X"4002", X"8300", X"8201", X"0500", X"8101", X"0602", X"4003", X"241E", X"0301", X"0102", X"2122", X"2021", X"0301", X"0102", X"2222", X"4001", X"0342", X"232B", X"0900", X"0302", X"0102", X"4002", X"0900", X"8201", X"2023", X"0303", X"2433", X"0301", X"4004", X"0301", X"1002", X"2137", X"2036", X"0301", X"0102", X"2237", X"4004", X"0304", X"4040", X"2500", X"2500", X"2500"

);

signal addr : std_logic_vector(8 downto 0);

begin

Rom_Proc : process ( Clk ) is begin

if ( rising_edge(Clk) ) then if ( Reset = '1' ) then addr '0'); do '0'); else addr

Reply to
Marco T.
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There is no hardware reason, why it shouldn't work, but most of the time CPLDs are smaller, so try to compile it for your CPLD to be sure it fits into the device.

BTW: Xilinx has some templates for ROM, RAM etc. If the (pure VHDL) code looks like the template, in FPGAs it is synthesized as BRAM. I've seen it somewhere on the Xilinx site.

For a CPLD maybe you can save some LUTs, if you don't clock your ROM, e.g. like this:

process begin case address is when "0000" => q q q

Reply to
Frank Buss

ROM is not a very efficient use of CPLD resources, but will work within teh size limitations. However be aware that as the synthesiser may be converting your ROM data into hardwired logic, it is quite likely that if you change the ROM data, it may no longer fit, or the timing may change significantly. Your data has a large proportion of 0 bits, and so is probably more amenable to ROMMing in a CPLD than the same amount of random data.

Reply to
Mike Harrison

They probably mean in the native hardware. You can certainly do small tables, they just get packed into product terms/macrocells.

If it compiled without errors, then it should be OK. You will get 'Unable to FIT' type messages if it faile. So look at the fitter report file, to see the product term usage per output.

Always a good idea to start with a small example, to verify the flow and constructs, and then expand it.

If speed is not critical, you can use a CPLD+SerialEEPROM as a Serial ROM/parallel output.

-jg

Reply to
Jim Granville

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