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RocketIO MGT Tile/Column Question

Dear all,

I am struggling to find the information I need from the Xilinx datasheet, perhaps someone could provide me with some pointers. I am working with a Virtex 4 FX100 in a FF1152 package. I have 20 MGTs to play with, arranged in 10 tiles numbered 101, 102, 103, 105, 106, 109,

110, 112, 113 and 114. These are further arranged into columns. There must be a simple method for determining which tiles are in which columns, but I haven't worked it out. Perhaps a related problem is that I have no idea where the odd numbering scheme comes from. Any help would be greatly appreciated.

TIA,

-- Peter

Reply to
Peter Mendham
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Table 7-3 is in the RocketIO manual (UG076 v3.0, May 23, 2006)...

/Mikhail

Reply to
MM

ADEPT shows the MGT map in Excel. The tool is freely available at

formatting link

Below is what you need to do:

  • Select and load Device
  • View->Display MGT
  • Excel->Show MGT Map in Excel

HTH, Jim

Peter Mendham wrote:

Reply to
Jim Wu

Thanks, after staring at that table for a long time (that was where I got the 101, 102 etc numbers from in the first place) I realised that the XnYm numbers were supposed to tell me that the tiles were split into two columns, where n is constant for a column. Whilst this seems blatantly obvious in retrospect, I can't see anywhere where it actually makes that clear.

Gripes aside, thanks for taking the time to point out the obvious :)

-- Peter

Reply to
Peter Mendham

Thanks, Jim. That diagram helped me decipher the datasheet and the table pointed out by another poster.

-- Peter

Reply to
Peter Mendham

I guess you never dealt with location constraints in Xilinx chips. Everything in recent Xilinx FPGA has its XY Cartesian coordinates. Among possible other places it is described in the Constraints Guide under LOC Description. You can also learn about this system by browsing through your design in either floorplanner or FPGA Editor.

/Mikhail

Reply to
MM

You're right. This is a prototyping board, and time constraints mean that I am developing the hardware in parallel with the guys doing the chip design. There is a bunch of stuff on the chip and they only just started to tackle the MGT side of things. All this means that 1) I have a pretty open remit and 2) I don't have the fullest idea of what I'm doing, as you suspected :)

Mind you, I would have thought that it was fairly common for the task to be split up in this way, with the chip and hw design being done by different people. Even if the vhdl was complete, it's not going to help the poor hw designer who has to grapple with that documentation. Just MHO.

-- Peter

Reply to
Peter Mendham

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