ROC PORT

CAN ANY BODY EXPLAIN ROC PORT AND GIVE SOME INFORMATION ABOUT? HOW CAN WE ACTIVATE IT IN OUR VHDL CODE? THANK YOU

Reply to
mahdi
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CAN ANY BODY EXPLAIN ROC PORT AND GIVE SOME INFORMATION ABOUT IT? HOW CAN WE ACTIVATE IT IN OUR VHDL CODE? THANK YOU

Reply to
mahdi

ROC is the reset-on-configuration block, that outputs a pulse just after device programming. It is automatically inserted in to the netlist post-synthesis.

To emulate this in simulation: (see the synthesis and verification guide)

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; library UNISIM; use UNISIM.all; entity EX_ROC is port ( CLOCK, ENABLE : in std_logic; CUP, CDOWN : out std_logic_vector (3 downto 0) ); end EX_ROC; architecture A of EX_ROC is signal GSR : std_logic; signal COUNT_UP, COUNT_DOWN : std_logic_vector (3 downto 0); component ROC port (O : out std_logic); end component; begin U1 : ROC port map (O => GSR); UP_COUNTER : process (CLOCK, ENABLE, GSR) begin if (GSR = '1') then COUNT_UP

Reply to
simon.charles

Thanks for your attention. This port is on xilinx fpgas. Is there an equvalent port on altera fpgas. Thanks

Reply to
mahdi

No. Reset must be provided externally. Altenatively it is safe to assume that all registers are 0 after configuration.

Best regards,

Ben

Reply to
Ben Twijnstra

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