RLOC problems

I'm playing around a bit with RLOC and I'm getting some weird results.

My top level file has these instantiations in it:

(* RLOC = "X0Y0" *) rloc_reg32 sourcefds(.clk_i(clk_i),.D(internal2),.Q(thebus)); (* RLOC = "X60Y0" *) rloc_reg32 destfds(.clk_i(clk_i),.D(thebus),.Q(internal4));

And rloc_reg32 looks like this:

module rloc_reg32(input clk_i, input [31:0] D, output [31:0] Q); (* RLOC = "X0Y0" *) FD fd00(.C(clk_i),.D(D[ 0]),.Q(Q[ 0])); (* RLOC = "X0Y0" *) FD fd01(.C(clk_i),.D(D[ 1]),.Q(Q[ 1])); (* RLOC = "X2Y0" *) FD fd02(.C(clk_i),.D(D[ 2]),.Q(Q[ 2])); (* RLOC = "X2Y0" *) FD fd03(.C(clk_i),.D(D[ 3]),.Q(Q[ 3])); (* RLOC = "X0Y2" *) FD fd04(.C(clk_i),.D(D[ 4]),.Q(Q[ 4])); (* RLOC = "X0Y2" *) FD fd05(.C(clk_i),.D(D[ 5]),.Q(Q[ 5])); (* RLOC = "X2Y2" *) FD fd06(.C(clk_i),.D(D[ 6]),.Q(Q[ 6])); (* RLOC = "X2Y2" *) FD fd07(.C(clk_i),.D(D[ 7]),.Q(Q[ 7])); (* RLOC = "X0Y4" *) FD fd08(.C(clk_i),.D(D[ 8]),.Q(Q[ 8])); (* RLOC = "X0Y4" *) FD fd09(.C(clk_i),.D(D[ 9]),.Q(Q[ 9])); // And so on... (* RLOC = "X0Y14" *) FD fd28(.C(clk_i),.D(D[28]),.Q(Q[28])); (* RLOC = "X0Y14" *) FD fd29(.C(clk_i),.D(D[29]),.Q(Q[29])); (* RLOC = "X2Y14" *) FD fd30(.C(clk_i),.D(D[30]),.Q(Q[30])); (* RLOC = "X2Y14" *) FD fd31(.C(clk_i),.D(D[31]),.Q(Q[31])); endmodule // rloc_reg32

Basically, I expect that I should be able to get two columns of CLBs with each CLB containing two flip flops.

However, if I look at the design the flip flops in "destfds" are not placed as I expect them to be. I have a screenshot of the placed design at

formatting link

. As you can see, the rloc_reg32 instance in the right has one CLB between the columns of flip flops whereas the instance to the left has no CLB between the columns of flip flops.

Have I misunderstood something about RLOC? I have tried to search the answer database at xilinx.com but haven't found anything which explains this. (I'm using ISE 8.1 if that matters.)

/Andreas

On 2006-09-06, Andreas Ehliar wrote:

I now noticed that I got the following error when opening the design in the FPGA editor:

ERROR:Place:346 - The components related to The RPM "hset" can not be placed in the required relative placement form

The following components are part of this structure: SLICEL thebus, placed to site SLICE_X4Y92 SLICEL thebus, placed to site SLICE_X4Y94 SLICEL thebus, placed to site SLICE_X4Y96 SLICEL thebus, placed to site SLICE_X4Y98 SLICEL thebus, placed to site SLICE_X4Y100 SLICEL thebus, placed to site SLICE_X6Y92 SLICEL thebus, placed to site SLICE_X6Y94 SLICEL thebus, placed to site SLICE_X6Y96 SLICEL thebus, placed to site SLICE_X6Y98 SLICEL thebus, placed to site SLICE_X6Y100 SLICEL internal4, placed to site SLICE_X72Y92 SLICEL internal4, placed to site SLICE_X72Y94 SLICEL internal4, placed to site SLICE_X72Y96 SLICEL internal4, placed to site SLICE_X72Y98 SLICEL internal4, placed to site SLICE_X72Y100 SLICEL internal4, placed to site SLICE_X76Y92 SLICEL internal4, placed to site SLICE_X76Y94 SLICEL internal4, placed to site SLICE_X76Y96 SLICEL internal4, placed to site SLICE_X76Y98 SLICEL internal4, placed to site SLICE_X76Y100 SLICEL thebus, placed to site SLICE_X4Y102 SLICEL thebus, placed to site SLICE_X4Y104 SLICEL thebus, placed to site SLICE_X4Y106 SLICEL thebus, placed to site SLICE_X6Y102 SLICEL thebus, placed to site SLICE_X6Y104 SLICEL thebus, placed to site SLICE_X6Y106 SLICEL internal4, placed to site SLICE_X72Y102 SLICEL internal4, placed to site SLICE_X72Y104 SLICEL internal4, placed to site SLICE_X72Y106 SLICEL internal4, placed to site SLICE_X76Y102 SLICEL internal4, placed to site SLICE_X76Y104 SLICEL internal4, placed to site SLICE_X76Y106

The reason for this issue is the following: All of the logic associated with this structure is already placed and the relative placement of the logic violates the structure. The problem was found between the relative placement of SLICEL thebus at site SLICE_X6Y100 and SLICEL internal4 at site SLICE_X72Y92.

Changing the RLOC constraint to X72Y0 instead of X70Y0 in the top level file seems to have corrected the problem. However I am kind of irritated that I didn't seem to get any error or warning message about this during place & route...

/Andreas