Hi, If I have a design module port that goes to both rising&falling edge FF, how do I constraint it in FPGA? In ASIC STA, I can use set_input_delay 0.2 -max -clock clk -clock_fall a set_input_delay 0.2 -add -max -clock clk a However, I don't see the clock_fall constraint from FPGA TAN.
Best regards, ABC