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Ripple counter ?

Hi,

I have a question concerning my multi-clock design.

A PLL is fed with a 30MHz external clock.

There are three different clocks generated by the PLL:

c0 : 48MHz (for internal use) c1 : 90MHz (for internal use) e0 : 90MHz (for external use)

Apart from that I have a clock divider which generates an

12MHz clock out of c0 and an inverted 90MHz clock out of c1.

When I compile the whole design I get the following warnings:

1.Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew Info: Detected ripple clock CLOCK_DIVIDER

Do I have to make some assignment for that? How?

I would appreciate your help.

Rgds André

Reply to
ALuPin
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Some additional thing:

The clock_divider is synchronous!

Rgds André

Reply to
ALuPin

I use QuartusII version 4.1 SP2

Reply to
ALuPin

Hello André,

Here is what you need to do:

1.- Define a Base Clock for your clock pin. This clock should have a requirement of 30MHz (Use Assignments->Settings->Timing Requirements and Options->Clocks)

2.- Define a derived clock for the CLOCK_DIVIDER. This clock should have the following characteristics:

- based on the base clock defined on the clock pin (Step 1)

- multiply Fmax by 2

- divide Fmax by 5 30 * 2 / 5 = 12

- Do NOT set any offset value. This will make the Timing Analyzer auto compute it.

(Use Assignments->Settings->Timing Requirements and Options->Clocks->New->Based On) Note that if there are any transfers between the pll input (30MHz) and the pll output (12MHz), the timing analyzer is likely to find a setup relationship (a requirement for this transfer).

That should be it. All PLL outputs do not need a clock setting as the Timing Analyzer auto generates them. The inverted clock out of c0 will also be processed correctly by the Timing Analyzer. Hope this helps.

- Subroto Datta Altera Corp.

Reply to
Subroto Datta

Hi Andre,

Just generate a new clock domain (12 MHz), and apply it to the output node of your clock divider. Quartus will stop yammering immediately.

It's good to have a whiny, grumpy timing analyzer ;-)

Best regards,

Ben

Reply to
Ben Twijnstra

Thank you for your help.

It is fine now.

Best regards

André

Reply to
ALuPin

Hello,

I have applied that clock setting and it seems to work.

One more question:

My PLL generates two clocks C0, C1 for internal use and a clock E for external use.

The problem: I have an external PHY which needs two clocks, one for data allignment and one for basic clock function.

Is it possible to route the E clock to two output pins ? I have tried to route to PLL2_OUT_p and to PLL2_OUT_n. I have made two different clock settings for that pins (device EP1C12F226C7 with pins J16: PLL2_OUT+ and K15: PLL2_OUT-) derived from the CLK_30 setting but the compiler complains that the design cannot be fit. The error message is the following: "Error: Can't place enhanced PLL pll1 in PLL location PLL_2 because PLL requires

2 external clock output ports but the PLL location only has 1 external clock outpit ports.

How can I solve this problem ?

Thank you for your help.

Rgds André

Reply to
ALuPin

Hi again,

I have thought about it ...

What about the option to route the output of the PLL to the PLL_OUT+ and PLL_OUT- ?

It would be no problem if my external PHY got differential clocks from the FPGA.

How do I have to make clock settings to get differential clocks?

Thank you for your help

Reply to
ALuPin

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