Hi, The VHDL standards community needs feedback from VHDL users.
Currently the Accellera VHDL TSC is working on enhancements to add classes/OO, Randomization constructs, and Functional Coverage with a goal of giving VHDL the same verification capability as SystemVerilog or E.
One of the VHDL simulation vendors has indicated that they only want to implement new features if the user community wants these features.
The questions come down to: Do you want these features added to VHDL? Do you want to VHDL to be capable of handling all of your testbench needs?
This work is work in progress and below is the current status. Keep in mind too that your interest/support of this work will help raise the focus and inspiration of those doing the work.
Classes / OO: Peter Ashenden submitted a class proposal last year and provided updates to it this year at DVCon. Currently he plans on finishing an updated draft soon.
Randomization: I just submitted the first draft of the randomization proposal.
Functional Coverage: I have started working on this - anyone else who is interested is welcome to contribute as much as they would like.
With a focused effort, like the one to finish the Accellera 3.0 draft of the standard, I think we can be done with these by September.
Although some have expressed doubt, it is clear that vendors will do what their user community asks them to do - otherwise, someone else will and, as a result, will earn your business.
You can post here, send your reply to me (let me know if I can use either your name and/or company name when I tally the results for the Accellera VHDL TSC), or join the Accellera VHDL TSC (which you can do as a non-Accellera member by registering) and post your reply there.
Thanks, Jim Lewis VHDL Evangelist SynthWorks VHDL Training