I'm working with a custom verilog core that accepts a small number of parameters, and I'm having a hard time pushing them through XST properly under EDK 8.1.
For example, I include the following line in my .mpd file:
PARAMETER C_DCR_BASEADDR=0b0001000000, DT=STD_LOGIC_VECTOR, BITWIDTH=10, MIN_SIZE=2, BUS=SDCR
But XST happily reports:
C_DCR_BASEADDR = 32'b00000000000000000000000001000000
Does anybody know how to ensure that my C_DCR_BASEADDR parameter is not initialized to something wider than 10 bits?