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Resource utilization broken down by hierarchy?

Hello,

I am interested in looking at the resource utilization of a design I am working on broken down based on the RTL hierarchy of the design. I am using a Virtex-II Pro part. I have seen in the past where you can do this using Floorplanner, however when I attempt to use Floorplanner on my design I get the following error....

"The design contains macros with RPM grid coordinates which are not supported by Floorplanner"

After digging a little in Xilinx's Answer Database, I don't believe that there is a way around this based on this answer....

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Specifically, this line.... NOTE: These solutions will not work if any of the cores have hardware multipliers because the RPM_GRID system must be used with multipliers.

I use hardware multipliers in my design.

Does anybody have any ideas as to how I could get my design in floorplanner, or another option for viewing the broken down resource utilization?

Thanks for all the help.

Regards, John

Reply to
paragon.john
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I use a program called Adept for this.

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Reply to
Barry

this.http://home.comcast.net/~jimwu88/tools/adept/

Thank looks promising, except I am using ISE 8.2 and it looks like Adept only supports 9.1 and 9.2. Any other ideas?

Thanks.

Reply to
paragon.john

You could try FPGAOptim

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- it's designed for just such a job (Full disclosure - I wrote it :-)

Please mail me if you want a copy. It allows me to keep track of who needs updates (a V5 updates is in the offing...)

Cheers, Martin

--
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
Reply to
Martin Thompson

A relatively simple method is to do individual synthesis & ngdbuild/map for your block(s) of interest. Be sure to prevent deletion of unused logic, and you probably won't want IO instances.

You can also use this method to get a reasonable estimate of achievable performance for the block by running through par.

JTW

Reply to
jtw

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