Hello,
I am trying to get acquainted with the amount of logic it takes to implement common structures to an FPGA. I built a simple VHDL 2x16bit memory like follows and targeted it to a xc4013 device (which includes block RAMs)
---- entity mem is port( Dr: in std_logic_vector(15 downto 0); wr: in std_logic; clock: in std_logic; clear: in std_logic; Rr: out std_logic_vector(15 downto 0); Ad: in std_logic_vector(1 downto 0) ); end mem;
------------------------------------------------------------------ architecture behv of mem is type ram_type is array (0 to 3) of std_logic_vector(15 downto 0); signal tmp_ram1_r: ram_type; begin process(clock, clear) begin if clear = '1' then -- do nothing elsif (clock='1' and clock'event) then if (wr='1') then tmp_ram1_r(conv_integer(Ad))