Hello all, I'm working on a FPGA design that runs in board with a Virtex-II that doesn't have any reset signal. I have some doubts about this.
On one side, It is supposed that everthing in the FPGA is clear after power up by GSR (please advise me if I'm confused). In this sense, I have read a paper wrote by Ken Chapman in TechXclusives that says that global reset is not needed in FPGAs.
On the other side, "Virtex-II Platform FPGA User Guide" says that GSR doesn't affect to SelectRAMs and shift registers and I have some doubts about DCMs as they should have an asynchronous reset.
So my questions are: 1. Can I use GSR as asynchronous global reset (including DCM)? If not, suggestions are welcome. 2. Is it better that I leave DCM RST to 0?
Regards, Daniel Gutierrez