Reset

As the name implies, an asynchronous reset resets the flip-flop or register immediately, without a clock. A synchronous reset input effectively forces the D input Low, sotat the flip-flop or register gets reset by the next clock, not immediately.

Synchronous resets, in conjunction with low-skew global clocks, result in the best predictive behavior.

But in certain special cases, you might need an asynchronous reset, to get the flip-flop reset before the next clock comes around. The penalty is less predictable, "sloppier" timing, especially if the asynchronous line has to drive many loads. Peter Alfke, Xilinx

NEVER (again: NEVER) use async resets on statemachines! Problem here is the "reset-release": you might end up with one FlipFlop in "normal operation" and another one still in "reset state" => your statemachine might change from "one hot" into "two (too?) hot" !!!

"Never" is a very strong word, and is almost never correct...

Asynchronous reset inputs are perfectly safe to use, and often necessary when circuit response must be guaranteed, even in the absence of a clock. However, they must be used carefully, controlling the release of reset (actually a synchronous event) such that it meets setup and hold relative to the clock.

What I recommend to resolve the release of reset problem is to synchronously release (deassert) the reset signal tied to the async reset inputs on the state registers. Note that the reset signal still asserts asynchronously, it only deasserts synchronously.

rst: process (rstin, clk) is begin if rstin = '1' then rstmeta

An important thing to remember is the 'others' clause in the case statement (missing from Andy's snippet above) that should always put the FSM to a default/reset state. Since FSM state registers are almost always one-hot encoded by FPGA synthesis tools, anytime it acquires an illegal value the FSM will be self-resetting thanks to such an 'others' clause.

Regards,

Alif.