Report for routing resource usage?

Hello all: Is there a way in Xilinx ISE of knowing the percentage of routing resources that have been utilized after Place and Routing? Until now I was happy just knowing if a design was routable or not. Now I need to have a more quantitive idea of the routing resource usage and I don't know where to start looking. The default Place and Route report gives only logic and I/O resource information. Thanks, Rafael Arce University of Puerto Rico

Reply to
raarce
Loading thread data ...

I too would love to see this Rafael. One of the other vendor's tools (Altera?) prints out the percentage of the FPGA devoted to routing so that you can see how much routing overhead there is, but what would really be useful is for the synthesizer to provide some idea as to what percentage of the resources are used by _each_ _module_. As it is now, I have to synthesize each module separately in order to obtain this information.

-- Ron

Reply to
Ron

I would really like to have a routing congestion map in the floorplan. I am sure the people that develop the algorithms have that implemented. Maybe it could be ported to ISE floorplanner?

Kolja Sulimma

Reply to
Kolja Sulimma

Hi Ron,

You are correct. Altera's Quartus II software will print out average and peak % utilization of routing.

There is also the "View Routing Congestion" option in the Timing Closure Floorplan Editor. This tool shows you graphically where routing congestion is occuring in your design, and which types of wires it is affecting.

Regards,

Paul Leventis Altera Corp.

Reply to
Paul Leventis

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.