remove logic redundancy

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Hello,

I'm developing a redundant design in ISE of Xilinx. When I simulate a
design the tool shows the following message :

Unit <csa4bits_tmr>: instances <csa1tmr>, <csa2tmr> of unit <add4csac>
are equivalent, second instance is removed.

I need that the tool doesn't remove the redundant logic. I want to
compare for exemplo a protected block with a umprotected block. I turn
off some features the tool but it did not efect.

I would like to know if there is option or some thing in ISE that
allows a redundant logic in a design because it is essential for me.

Sorry   (bad english)

thank you ..


Re: remove logic redundancy
The tool is smart enough to know that you're not going to use it, so it
removes the redundant blocks.

snipped-for-privacy@gmail.com wrote:
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Re: remove logic redundancy
Marlboro a E9%crit :

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This is utterly wrong (besides, never rely too much on the tool's
smartness). The tool simply sees that the two logic constructs have the
same inputs and the same behaviour so it removes one of them.
I haven't used ISE in some time but I know for sure that there is an
option somewhere to keep it from removing redundant or equivalent
logic. Or maybe it is an attribute. Search for "preserve" in the
documentation.

Nicolas


Re: remove logic redundancy
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What's about the output? If you don't have an output then the tool
knows that you not gonna use it.  As a result, it will remove the
redundance.  Sometimes I ran into this too, what I did was making up a
dummy output for the second logic

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That rings a bell
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Re: remove logic redundancy
Look up the keywords:

SAVE
KEEP

If two identical blocks (including inputs) have each an output, if
recognised, the logic is removed for one, and both outputs are driven
from the remaining block.

Why would you want to have two blocks that did exactly the same thing?

With fully buffered interconnect, there is no delay penalty.

Austin

Re: remove logic redundancy
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To detect and/or mitigate against SEUs?
Cheers, Syms.



Re: remove logic redundancy

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In which case, you should either use the TMR Tool(tm), or be very very
careful (not recommended without help from Xilinx).  Many people have
tried to perform manual methods to perform such mitigation, but without
knowledge of how the tools work, and how the hardware actually works
(not the fantasy presented by FPGA Editor), they all fail miserably.

Even the experts can make mistakes, and find their design has worse
performance than an unmitigated one (adding anything at all, increases
the failure rate, unless done properly).

If anyone is serious about mitigation (in spite of the excellent SEU FIT
rates -- 10 to 30 times BETTER than an equivalent 90 or 65nm ASIC or
ASSP*), then I suggest you work with your disti or Xilinx FAE, who knows
how to do it.

Austin

* Don't take my word for it, look it up for yourself.  At SELSE II
(2006), the industry consensus was ~1000 FIT/Mb for logic AND SRAM at
90nm and below for ASIC and ASSP.  We publish our FIT rates.  And you
can see them anytime.  If you really want FIT rates in the single
digits, you have techniques in our FPGAs to get there (TMR, ECC, etc.).

Re: remove logic redundancy

Marlboro a E9%crit :

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Ah sorry, in that case this is perfectly right.
But I think the OP was talking about replicated logic with its outputs
used.

Nicolas


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